What I like:
- Successful HFET demonstration
- No fundamental show-stoppers
- VCSEL working in principle
- Confidence in the roadmap, but see below
- Confidence in progress in the lab to fab to commercialization
What I don't like:
- Missing explanation on the 250 nm effective gate length. Readers might ask: Hey, haven't we been down to 40 nm already?
- Delays in completing the VCSEL milestone due to required optimization
- Unclear language on what has been achieved on the VCSEL and what is still to be done
- Unclear time frame: "over the next couple of months". Talking about confidence in the roadmap and about delays at the same time is contradictory. Either you can meet your roadmap targets, then (by definition) you don't have any delays. Or you have delays, then you are either unable to meet your roadmap targets or you have a strategy to catch up the delays. – Let's remember POET's Q3 target: "Tape out first transceiver prototype – First pass design for 10 Gbps and 25 Gbps transceivers". Simple question: Will POET Technology be able to hold this milestone or not? Based on this news release, I am unable to answer it.
As I mentioned before, I am confident that POET will be able to deliver the integrated VCSEL transceiver sooner or later, but I am unhappy with their communications.
