It is important to understand that the Optical Interposer is applicable to a very wide spectrum of wavelength and that the POET GaAs platform is applicable primarily from 850nm to 980nm however that range can be expanded with quantum dot sizing adjustments.  

There is, as many of  us are keenly aware a very large library of patents that exist on the POET GaAs platform representing Geoff’s life work. A very widespread diversity of applications contained within the 1000's of pages of Geoff Taylors patents assigned to POET. Everything from memory and single electron transistor applicable to quantum physics to image capture and readout applications. And potentially single mode capabilities.

It is interesting that Geoff continues the work as indicated by the Oct 30, 2018 patent. I have long suspected that the issue(s) related to the 4 terminal operation of  the thyristor were associated with the ability to  selectively and accurately go  through the high temperature anneal.

It is not something I would devote time and effort to explore right now but it is something that may be waiting for us in the future.

Integrated circuit implementing a VCSEL array or VCSEL device 

Abstract

A semiconductor device includes an array of VCSEL devices with an annealed oxygen implant region (annealed at a temperature greater than 800.degree. C.) that surrounds and extends laterally between the VCSEL devices. A common anode and a common cathode can be electrically coupled to the VCSEL devices, with the common anode overlying the annealed oxygen implant region. The annealed oxygen implant region can funnel current into active optical regions of the VCSEL devices and provide current isolation between the VCSEL devices while avoiding an isolation etch between VCSEL devices. In another embodiment, a semiconductor device includes an annealed oxygen implant region surrounding a VCSEL device. The VCSEL device(s) can be formed from a multi-junction layer structure where built-in hole charge Q.sub.p for an intermediate p-type layer relative to built-in electron charge Q.sub.n for a bottom n-type layer is configured for diode-like current-voltage characteristics of the VCSEL device(s).

http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.htm&r=1&p=1&f=G&l=50&d=PTXT&S1=taylor-geoff-w.INNM.&OS=in/taylor-geoff-w&RS=IN/taylor-geoff-w