Aiming to become the global leader in chip-scale photonic solutions by deploying Optical Interposer technology to enable the seamless integration of electronics and photonics for a broad range of vertical market applications

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Message: Re: DIE TESTING... WAS: Re: Patent: METHOD OF FORMING AN HERMETIC SEAL ON ELECTRONIC AND OPTOELECTRONIC PACKAGES

See my previous post. The one thing we don't know is whether POET is applying design redundancy such that failure of one path does not fail the entire optical engine (n+1 redundancy).

But the short answer is failed optical engines are identified and discarded. Also remember 400 optical engines per wafer.

In some cases once high yield is obtained for a particular design then wafer level testing is no longer required as time and cost of the water level test is no longer more economic than packaging all optical engines including failed chip sets.  In other words discarding of a small number of finished products becomes cheaper than the water level testing step. However since POET has found a very fast way of testing the optical engines that does not require external light source testers then I expect that they will always test each engine before packaging especially when very high capacity and more complex optical engines are built.

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