Oz > This statement isn’t correct “In some cases once high yield is obtained for a particular design then wafer level testing is no longer required as time and cost of the wafer level test is no longer more economic than packaging all optical engines including failed chip sets.”   

That was meant to be a general statement about wafer level testing that I don’t think would be applicable to POET as I further explained.

To compare apples to oranges it is fair to remind people that the active optical and electronic elements…lasers, detectors, modulators etc. are already tested and determined to be of known good die before they are assembled into the optical engine. I expect that the testing is more about meeting the expected coupling efficiency threshold to match the power output and input of the active elements.  So in terms of yield I think POET has a big advantage because of the fact that with silicon photonics everything except for the laser is being fabricated on the wafer and is being tested for the first time.

But the point I wanted to make is that POET’s wafer level testing should be very quick and low cost so my expectation is that wafer testing will always be performed. And I have not spent enough time looking at the detail in the patent but I expect that the hermetic seal will also be a wafer level process where all optical engines will be packaged at once despite a pass or not pass instance for an individual engine.