As per the latest published patent (thanks Guernsey) which is an extension of the associated granted patent.

https://agoracom.com/ir/POETTechnologies/forums/discussion/topics/745821-patent-publication/messages/2280357#message

It is interesting to observe the number of configurations that are presented in these patents. A number of the embodiments contain integrated electrical devices within the substrate on which the optical interposer/dielectric stack is deposited.

These integrated electrical devices are described in a number of ways within the these embodiments with the following functions provided (examples): signal  processing, signal conditioning, signal generation, memory, and computation.

Referring to FIG. 7A-7B, cross sectional schematics of embodiments of the inventive optical dielectric interposer 700 and sub mount assembly 705 are shown. In FIG. 7A, an embodiment for interposer 700 includes substrate 710, interconnect layer 720, inventive planar dielectric stack structure 740 disposed on interconnect layer 720, and integrated electrical device 764. In some embodiments, integrated electrical device 764 in the underlying substrate 710 is a transistor, capacitor, resistor, inductor, or other electrical device. In other embodiments, integrated electrical device 764 is a p-channel metal oxide semiconductor (PMOS) transistor, an n-channel metal oxide semiconductor (NMOS) transistor device or array of one or more of these devices. In some embodiments, the electrical device 764 is an array of transistor devices based on complementary metal oxide semiconductor (CMOS) technology. In some embodiments, transistor arrays 764 in the substrate 710, are used for signal processing, signal conditioning, signal generation, memory, and computation, for example.

In some embodiments, optoelectrical die 760 are connected to one or more of electrical devices 764 via metal lines 726 in the interconnect layer 720. In these embodiments, the optical signals may also originate, wholly or in part, on the sub mount assembly 705 from which the signals can be transmitted through the planar waveguide structures 740 to the optical fiber 790.

In some embodiments, integrated electrical device 864 in the underlying substrate 810 is a transistor, capacitor, resistor, inductor, or other electrical device. In other embodiments, integrated electrical device 864 is a p-channel metal oxide semiconductor (PMOS) or n-channel metal oxide semiconductor (NMOS) device, or array of one or more of these devices. In other embodiments, electrical device 864 is an array of transistors based on complementary metal oxide semiconductor  signal processing, signal conditioning, signal generation, memory, and computation, for example.

Integrated electrical device 964 in underlying substrate 910, in some embodiments, is one or more of a transistor, capacitor, resistor, inductor, or other electrical device, or array of electrical devices. In other embodiments, integrated electrical device 964 is a p-channel metal oxide semiconductor (PMOS) transistor or an n-channel metal oxide semiconductor (NMOS) device, or array of one or more of these devices. In yet other embodiments, device 964 is an array of transistors based on complementary metal oxide semiconductor (CMOS) transistor technology. In yet other embodiments, the integrated electrical device 964 is a bipolar transistor or an array of bipolar transistor devices. In yet other embodiments, the integrated electrical device 964 is a field effect transistor or an array of field effect transistors. In some embodiments, transistor arrays 964 in the substrate 910, are used for signal processing, signal conditioning, signal generation, memory, and computation, for example.

In providing step 1000, a substrate is provided with one or more optoelectrical or electrical devices coupled to an interconnection layer. In embodiments, these devices are one or more of a transistor, capacitor, resistor, inductor, or other electrical device, or an array of one or more electrical devices. In other embodiments, these devices are one or more of a p-channel metal oxide semiconductor (PMOS) transistor and an n-channel metal oxide semiconductor (NMOS) device or devices. In yet other embodiments, the devices are an array of transistors based on complementary metal oxide semiconductor (CMOS) transistors technology. In yet other embodiments, the one or more devices coupled to the interconnection layer as described in providing step 1000 in FIG. 10A is a bipolar transistor, two or more bipolar transistors, or an array of bipolar transistor devices. In yet other embodiments, the one or more devices is a field effect transistor, two or more field effect transistors, or an array of field effect transistors. In some embodiments, transistor arrays coupled to the interconnect layer are used for signal processing, signal conditioning, signal generation, memory, and computation, for example.