A correction from my previous post where I referenced 400 optical engines fit on a 8 in wafer. That is now reported as greater than 500 optical engines for a 400G. So back to the point. When POET moves to 12 in silicon the advantages become greatly increased when we look at wafer scale assembly. For example  the die attach process  allows for the dies being attached to  the interposer bonding pads to go  through a short cut because of the self-aligning mating features between  the interposer sub-mounts and the die pads.

Let me explain my understanding. For anyone who has done some soldering you will get it right away. When you solder wire or copper tubing it is important to get the temperatures high enough to allow the solder to flow. At the right temperatures the solder is sucked into the connection like magic seemingly defying gravity. If you don’t get all contact point temperatures high enough you end up with the metals being tacked together and a very poor connection/bond.

So in the case of POET and any flip chip application the solder has a very low melting point. What POET has done (as I understand) is to tack all the die in temporary positions above the self-aligning mating points on the interposer sub-mounts and this is done during the  pick and place with each die tacked into  place by a laser. Assumptions based on patent information is that each die  takes 1 second  to place and 6 seconds to tack into the temporary position  between the mating points. The next step is to melt the low temperature solder bumps across the entire wafer to a point where the solder flows very freely and the dies are sucked into place by surface density to rest on the highly accurate stops (the mating points). This reflow step takes approximately 60 seconds. At this point the dies have been accurately and permanently fixed in place. So we can appreciate that the larger the wafer the faster the throughput will be. At some point when POET moves from 8 inch to 12 inch throughput increases significantly and costs drop even further. Now the CAPEX of course would increase significantly as 12 in wafer capacity is in demand as opposed to the capacity that is available at 8 in.

in the wafer-level semiconductor die attachment method, the steps of placing a semiconductor die over a sub-mount and heating the first portion of the solder layer that is in contact with the die pad of the semiconductor die are performed for a single semiconductor die at a time until each of the sub-mounts 204 has one or more semiconductor dies temporality held thereon. However, the reflow process for attaching the semiconductor dies 220 to the corresponding sub-mount of the sub-mounts 204 is performed at wafer-level in contrast to the conventional semiconductor die attachment method, where each sub-mount is reflowed separately. Based on the assumption that the die placement time is 1 second, the heating time for temporary holding the semiconductor dies 220 is 6 seconds, the reflow time is 60 seconds, and the dicing time is 1 second, the time required for obtaining 1,000 die attached sub-mount packages amounts to 8,059 seconds, i.e., 2.23 hours. Hence, the wafer-level semiconductor die attachment method saves almost 72 percent of time in comparison to the conventional semiconductor die attachment method, thereby reducing the cost of optoelectronic packaging and improving the process efficiency and the process throughput.

[0060] At step 510, the pre-singulated wafer 202, having the semiconductor dies 220 temporarily held at the corresponding initial placement positions, is reflowed. During the reflow, the solder layer of each sub-mount of the sub-mounts 204 melts, and introduces the self-alignment restoring force. Under the influence of the self-alignment restoring force, each semiconductor die of the semiconductor dies 220 slides in lateral and vertically-downward direction from the corresponding initial placement position to a corresponding final placement position. Each semiconductor die continues to slide in the lateral and vertically-downward direction until the corresponding die mating features come in contact with the sub-mount mating features of the corresponding sub-mount. Thus, each semiconductor die stops sliding, when the corresponding die mating features come in contact with the sub-mount mating features of the corresponding sub-mount.