Aiming to become the global leader in chip-scale photonic solutions by deploying Optical Interposer technology to enable the seamless integration of electronics and photonics for a broad range of vertical market applications

Free
Message: New Patent Application

US20210215876 - METHODS FOR OPTICAL DIELECTRIC WAVEGUIDE STRUCTURES

https://patentscope.wipo.int/search/en/detail.jsf?docId=US330899425&tab=NATIONALBIBLIO&_cid=P11-KRCDMR-85529-1

Office

United States of America

 Application Number

17215355

 Application Date

29.03.2021

 Publication Number

20210215876

 Publication Date

15.07.2021

 Applicants

POET Technologies, Inc.

 Inventors

William Ring

Suresh Venkatesan

 

Abstract

(EN)

An optical subassembly includes a planar dielectric waveguide structure that is deposited at temperatures below 400 C. The waveguide provides low film stress and low optical signal loss. Optical and electrical devices mounted onto the subassembly are aligned to planar optical waveguides using alignment marks and stops. Optical signals are delivered to the submount assembly via optical fibers. The dielectric stack structure used to fabricate the waveguide provides cavity walls that produce a cavity, within which optical, optoelectronic, and electronic devices can be mounted. The dielectric stack is deposited on an interconnect layer on a substrate, and the intermetal dielectric can contain thermally conductive dielectric layers to provide pathways for heat dissipation from heat generating optoelectronic devices such as lasers.

 

 This latest application is a continuation of previous work, and with it the number of patents and patents pending related to the OI and dielectric waveguide structure continues to grow.  Since 2018, there have been at least 8 related patents granted, and more in the works.  The following list patents and applications directly related to the OI and dielectric structures:

 

US Patent Office – Patents granted

   
       

Patent #

Filed

Granted

Inventor

10,983,277

18-Jan-20

21-Apr-21

Ring, Florjanczyk

10,976,497

25-Sep-19

13-Apr-21

Venkatesan, Florjanczyk, Hall, Liu, Yang

10,976,496

6-Aug-19

13-Apr-21

Venkatesan, Florjanczyk, Hall, Liu, Yang

10,962,715

16-Jul-18

30-Mar-21

Ring, Venkatesan

10,795,079

16-Jul-18

6-Oct-20

Venkatesan, Lam

10,718,905

25-Jan-19

21-Jul-20

Ring, Florjanczyk, Venkatesan

10,663,660

16-Jul-18

26-May-20

Venkatesan, Lam

10,551,561

16-Jul-18

4-Feb-20

Ring, Florjanczyk

         

 

 

WIPO – Patent applications

   
     

Application #

Date

Inventor

17215355

15-Jul-21

Ring, Venkatesan

17034246

18-Mar-21

Venkatesan, Lam

16932970

5-Nov-20

Ring, Florjanczyk, Venkatesan

16876059

13-Aug-20

Venkatesan, Lam

16258292

5-Sep-19

Ring, Florjanczyk, Venkatesan

16036208

8-Aug-19

Venkatesan, Lam

16036151

25-Jul-19

Ring, Florjanczyk

16036234

25-Jul-19

Venkatesan, Lam

16036179

25-Jul-19

Ring, Venkatesan

       

 

 

 Though quite technical in nature, one can read through this latest one and at least get a feel of the power and versatility of the invention.  The features noted below will familiar to most, but for some of the newer folk may be useful:

 ·         The stack itself can be altered in any manner of ways to achieve new properties or add features.  Planar optical waveguides offer significant reduction in optoelectronic package size by eliminating free space optics. 

 ·         Integrated waveguide structures also allow for the formation of optical device structures, such as filters, gratings, and spot size converters, for example, directly onto the substrate. 

 ·         Planar optical waveguide structure for transmission and routing of optical signals in photonic integrated circuits that has low optical loss, has low stress, is compact, and is economically manufacturable. 

 ·         The dielectric waveguide structure transmits optical signals with low loss (In some cases, loss is much less than 0.5 db/cm), is integrated into a substrate and thereby reduces fabrication costs, is deposited at low processing temperatures so is fabricated with low stress to prevent stress-induced delamination of the film structure and deformation of the substrate. The invention provides superior optical and mechanical performance and provides superior economic benefits in comparison to the current state of the art. 

 ·         Integrated electrical device in the underlying substrate, may be one or more of a transistor, capacitor, resistor, inductor, or other electrical device, or array of electrical devices.  Integrated electrical device may be a (PMOS) transistor or an n-channel metal oxide semiconductor (NMOS) device, or array of one or more of these devices; or, is an array of transistors based on complementary metal oxide semiconductor (CMOS) transistor technology; or, is a bipolar transistor or an array of bipolar transistor devices; or, is a field effect transistor or an array of field effect transistors. Transistor arrays in the substrate may be used for signal processing, signal conditioning, signal generation, memory, and computation. 

 ·         Integrated patterned waveguide structures include filters, arrayed waveguides, gratings, multiplexers. demultiplexers, spot size converters, power combiners, etc.  An additional devices may be either a photodiode for receiving optical signals transmitted through the waveguide and subsequently converting the optical signals to electrical signals that are delivered to the interconnect layer, or a sending device, for example, such as a laser for converting electrical signals from the interconnect layer, for example, to optical signals for transmission to the waveguide.

 ·         Alignment features such as marks, physical stops or v-grooves can be incorporated into the device for very accurate placement of various optical die, devices and fibers.  Permits high volume manufacturing

 ·         Invention permits insertion of thermally conductive dielectric layer for to provide effective heat dissipation pathways from heat generating optoelectronic devices (ie lasers).

 ·         Invention permits addition of a hermetic seal to create a capped optoelectronic package to protect the sub mount assembly within the cavity.

By no means a complete list...

Share
New Message
Please login to post a reply