One key point that Andrew Rickman (Rockley CEO) makes during the Bernstein CGM Disruptors Conference 11/19/2021 is that the challenge has been to miniaturize the technology re: medical wearables.

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My comment: One of POET’s strengths is the small footprint of their devices. As Suresh has stated this ability to fit more devices in a given space allows for new innovations and products which have never before been available. Again it is all about the waveguide and the simplicity of the design when compared to the limitations associated with deep etching required to reach the cladding layer of the SIO wafer(Silicon on Insulator) The waveguides are deeply buried. POET of course uses the optical interposer to produce multilevel waveguides in a dielectric stack that is deposited on the surface of the low cost bulk silicon wafer. An architecture that allows for an ease of design that can’t be matched in typical silicon photonics applications.

$400 million in funding and 7 years of development.

If we look at Rockley’s roadmap we can see that they are at the pre-alpha stage. And are working towards products in the market in 2023. Next year is primarily NRE income (they are forecasting $63 million in NRE funding in 2022) first product revenue from unregulated devices expected in 2023. Regulated medical devices integrated into consumer products that produce actionable information such as glucose monitoring requires FDA approvals and non regulated device claims of accuracy is also under FDA scrutiny. 

Andrew: we are on the road to the final version for scale up production which occurs in Q4 of next year. So you'll see the product increasing kind of in presence, in the marketplace. We are basically gearing up to manufacture for our customers in the consumer area to bring their products to market in 2023. It's really two parallel paths here. With a consumer oriented device that would not be kind of FDA approved for glucose readings and then a medical device that might ultimately get there.

So let's dig a little deeper. 

EPIC Online Technology Meeting on Automated Packaging & Testing of Photonic Integrated Circuits held in October but reloaded to Youtube on Dec 8 (due to freezing) as requested by one of POET’s very diligent large shareholders.

EPIC Online Technology Meeting on Automated Packaging & Testing of Photonic Integrated Circuits - YouTube

Time 1:20

Rockley Photonics…Cyriel Minkenberg Director, Product Management at Rockley Photonics

I just want to mention for those who are not aware that at Rockley Photonics we have, you know pivoted from addressing the com space to basically biosensing so the key offering that we’re driving towards is basically to compliment the existing ppg based led sensor in consumer wearables with the type of spectrophotometer leveraging dozens of lasers integrated on a on a single pic to enable monitoring various biomarkers that you know with regular LED’s you can’t do.

We have not said anything publicly about the product that we're pursuing in this space. 

My comment: As per Andrew Richman Rockley has not publicly disclosed any metrics associated with their pre-alpha samples.

 What I will say is that you know in terms of the process technology as well as the packaging technology.Uhm, I know a lot of that has in fact been developed with the initially with the comms focus, but luckily you know most of that also translates to the sensing space.

So we have a proprietary silicon photonics process that we license out to our foundry partners. It's based on on thick waveguides as opposed to the the submicron waveguides that most other people in this space are pursuing.I know that is actually fairly well positioned to scale, as it leverages, you know a lot of mature CMOS processes.On the three five side you know, we also partner with with foundries who implement our own laser SOA and modulator designs. Which are custom to Rockley. So we have a certain process optimizations there to work very closely with our foundries to make sure that you know what we get in terms of the III-V matches are specific silicon photonics platform for the electronic IC’s we follow a more conventional foundry process.

My comment: Rockley’s waveguides are 3 microns (as stated in the presentation) while POET’s dual core waveguides are as large as 8 to 10 microns at the lowest level to closely match the sizing of single mode fiber and tapers to  an upper waveguide which can be .5 microns. 

POET patent info (granted):

The thickness of the upper single mode waveguide of the dual core waveguide, in embodiments, affects the extent of the coupling of the optical signals between the upper and lower waveguides. For upper waveguide thicknesses of approximately 0.5 microns, optical signals are primarily carried in the lower waveguide core, but can be loosely coupled to the thin upper core. An increase in the thickness of the upper waveguide core to thicknesses of approximately 1-3 microns, for example, with the introduction of a tapered upper waveguide section, enables transitioning of the optical signals to the upper waveguide core, and enables single mode propagation in the upper core substantially independent of the propagation in the lower core.

In embodiments, the upper waveguide core is increased in thickness through tapered portions of the optical device circuit to provide the required thickness in the upper core of the dual core waveguides. These regions of increased thickness in the upper core of the dual waveguide structure allow for more reliable processing of the optical signals for such tasks as multiplexing and demultiplexing, among others, particularly in optical waveguide structures containing bends and curvature. Curvature in the optical waveguides is necessary for, and allows for, the creation of optical device structures such as arrayed waveguides that facilitate optical signal processing.

The tapering of the waveguides in the vertical direction, hereafter referred to as vertical tapering, provides one approach for the formation of an adiabatic transition region for moving the signal from the thick bottom core to the thinner upper core of the dual core waveguide structure. In other embodiments, lateral tapering, or tapering in the horizontal direction perpendicular to the receiving facet of the thick lower waveguide core is used in addition to the vertical tapering of the upper core. Additionally, the vertical tapering can vary linearly, nearly linearly, super-linearly, or sub-linearly with the length of the tapered section to transition the optical signal from the lower core to the upper core of the dual core waveguide.

In embodiments, a receiving portion of the dual core waveguide is fabricated from the combination of a lower waveguide of approximately 8-10 microns in thickness with a thin, upper waveguide core of approximately 0.5 micron in thickness. This receiving section is substantially thickness matched to an incoming optical fiber of approximately 8-10 microns in thickness or to the thickness of an optoelectronic device and receives signals from the optical fibers or optoelectronic devices that are mounted in proximity to a receiving end or facet of the dual core waveguide structure. In these and other embodiments, the receiving portion guides optical signals to a tapered portion through which the optical signals are substantially transitioned to a thick upper core of approximately 1-3 microns of the dual core waveguide.

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Back to EPIC conference Rockley presentation 

For the bonding, you know this is a very big one. You know in in comms you have maybe 4 lasers on a die, but in these new kind of pics for our sensing applications we're going to have dozens.So clearly the throughput of the bonding process needs to be increased dramatically, so this is this is a very big one for us, and here we are moving from die to die bonding to die to wafer level bonding. 

Burn in is a very big one as well. That's going to be extremely challenging at the wafer level. We believe that the you know the overall level of you know heat that you need to dissipate. If you're burning in, you know hundreds of pics.With dozens of lasers on them at the same time at wafer level, that's going to be extremely challenging, so I think that that's definitely an area where we also need to rely on partners to to get to where we need to be

For instance for the testing the probes. You know the electrical probes, optical probes, perhaps even combined probes. You know there you need to custom design them.

So just to to highlight a couple of things that we need in terms of, you know the processing capabilities for for assembly

We also rely on on wire bonding actually to couple the IC’s to the pics, so we need highly reliable short and low loop wire bonds for high speed performance.

We found that this type of integration is actually the most cost effective while still delivering the kind of performance that you need. However, going forward in the com space, we believe that you know 3D integration or two and a half the integration type.Solutions are going to be needed to keep scaling the lane. The lane rate for fiber attach

My comment: This comes to the heart of the matter in my opinion. With Suresh’s background as the Senior Vice President, Technology Development at GLOBALFOUNDRIES he is equipped with the expertise and experience to identify the packaging evolution in the semiconductor space applied to the development of the most advanced packaging systems being used today in mobile device applications.

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