Exactly Rogue,

from the article: Under this collaboration, standard CMOS wafers that implement silicon photonics chips will be post processed using EVG's NIL technology to implement optical elements such as mirrors and lenses for Teramount's unique "self-aligning optics".

So, adding optical elements and fibre attach after the fact; therefore, a completely separate fabrication and testing step required in order to create a finished optical engine for optical engine supplier X.  Seems like a lot of extra work compared to POET's all inclusive wafer scale and testing of the prepackaged all-in-one product.