Here is a recap from Synopsys blog on their website 

2022 Synopsys Photonic Symposium 

https://blogs.synopsys.com/optical-solutions/2022/11/21/2022-synopsys-photonic-symposium-recap/

The next speaker, Dr. Suresh Venkatesan, CEO of POET Technologies, introduced POET’s ideas for extending wafer-level chip scale packaging to photonic systems. POET sees assembling, packaging and testing billions of complex heterogeneous systems as a main industry challenge. They are leveraging the idea of heterogeneous integration of best-of-bread chiplets using a common interposer with both electronic and photonic connections. An interposer enables complex systems to be built with a known good die, with interposer interconnect testing being done at the wafer level.

The main idea is to extend the concept of an electrical interposer by adding photonic connections. This has the benefit of eliminating wire-bonds and reducing power consumption and parasitics between chiplets. POET calls this a Photonic Interposer. All processing is done on full wafers, hundreds at a time, in an automated process. The photonic interposer has both electrical and optical layers and can be processed on either 8-inch or 12-inch wafers. A hybrid integration of electrical and photonic chiplets on the interposer is what POET calls an Optical Engine.

A key benefit of this solution is that it uses conventional flip-chip processing technology. Passive electrical and photonic components are printed on the silicon interposer, while active components use hybrid integration as chiplets onto the interposer. The photonic interposer supports two non-interacting optical waveguide layers sandwiched between electrical layers. Light can be coupled in and out, either vertically or horizontally. The technology supports through-silicon-vias (TSVs), so both sides of the interposer can be used. POET has also architected in thermal isolation and management into the photonic interposer to move heat away from sensitive photonic elements such as lasers and resonant devices. Venkatesan showed examples of small-form-factor 100G and 400G transceivers with spatial division multiplexing from 8 to 16 channels running from 1.6 Tbps to 3.2 Tbps, representing a 75% reduction in size compared to designs using discreet components. Venkatesan also pointed out that signal integrity is much better due to lack of wire bonds and metal traces. Since the signal integrity is better, POET is now investigating the idea of removing the DSP altogether, which has the potential to eliminate 6 to 8 watts of power consumed by the DSP.