As per that Vanguard-Automation and Ligentec NR: edge couplers available in the LIGENTEC PDK, Vanguard Automation and LIGENTEC have achieved seamless connectivity between an SMF fiber array and SiN PICs. A total insertion loss of less than 1.5 dB has been demonstrated. 

That is a good number but it still falls short of what POET’s butt coupling achieves without a photonic wire bond. The waveguide design is a large factor.

POET VLSI Paper - Hybrid Integration

Results and Discussion: Waveguides: Our waveguides are designed to both be CMOS compatible and provide low loss characteristics. The material loss through the waveguides characterized by prism spectroscopy is <0.3dB/cm and is about one order of magnitude better than typically observed in small core silicon waveguides used in most other silicon photonics technologies. Moreover, our waveguides are largely athermal (dn/dT=12pm/°C) and are non-birefringent. A proprietary Spot Size Converter has been designed for chip facet fiber coupling achieving facet coupling losses of 0.25dB. Optical Passive device performance: Waveguides must be designed and configured into high performance optical passive devices for use in any optical application. Multiplexers and Demultiplexers form the backbone of any direct detect data communications WDM (wavelength division multiplexing) system. These devices have to be precisely engineered for the required bandwidth spectrum used (for example, FR4, LR4). Fig.4 shows the measured optical spectrum for the passive demux/mux devices built on the Optical Interposer for FR4 and LR4 systems respectively. Excellent insertion loss, crosstalk, channel uniformity are achieved exceeding requirements. Vertical Mirrors: In addition to in plane coupling of light, POET’s optical interposers utilize vertical mirrors to enable out of plane coupling. The vertical mirrors are used with topentry photodetectors and for wafer level test. Fig. 5 shows the construction and performance (0.5dB coupling loss) achieved by the vertical mirrors when coupled to a PD

https://poet-technologies.com/docs/presentations/VLSI-IEEE%20Symposium%20Accepted%20Paper%20on%20Wafer-Scale%20Hybrid%20Integration%20-%20June%2016%202022.pdf