I took a quick look at the LIGENTEC SA website technology overview page.

State of the art silicon nitride platform.

SOI waveguides (SOI wafer) deep etching with very low waveguide propagation loss. 

Coupling to single mode fiber (<1dB/facet)

Innovations in development:

Integration of Lithium Niobate modulators (LNOI)

Photodiode integration 

Gain materials

Other

So that is the starting point. A very well developed set of devices with an apparent wide range of applications in a monolithic architecture with local cladding remaining open for sensing and bonding. No optical interposer. No integrated photodiode (under development) which is no doubt a big challenge with SOI deep etch requirements.  POET’s flip chip photodiode provided best in class coupling at .5dB and was the first 800G offering (those coupling numbers are two years old and have likely improved with vertical mirror refinements)..  Also of note that Ligentec requires a high efficiency heater module for thermo-optic tuning…in other words not athermal utilizing microring resonators which must be maintained at set temperature.

Vanguard application from Vanguard website:

Our research partners at KIT have demonstrated that photonic wire bonds can connect to a wide variety of on-chip waveguides and optical fibers [1] – [4]. For chip-to-chip connections, lateral dimensions of PWB waveguides typically amount to 1…2 µm, and the pitch can be smaller than 5 µm, enabling hundreds of PWB per millimeter of chip edge [1]. For a connection of two silicon-on-insulator (SOI) waveguides, insertion losses of 1 dB … 2 dB have been demonstrated with negligible variation in the wavelength range 1200 nm … 1600 nm [1]. Similar loss figures are obtained when connecting PWB to multi-core fibers (MCF) [2] or to InP-based laser sources [3], [4].

My opinion/observations. POET is starting out with excellent numbers for both fiber coupling and out of plane coupling. Thus it is hard to improve on those numbers. My observation is that the Optical Interposer has significant structural capabilities which is beneficially located at the surface of the bulk silicon wafer. As such it has allowed POET to focus their attention on detailed interlocking features that are fabricated to  nanometer scale tolerance achieving precise placement for efficient coupling in terms of flip chip applications (as noted in previous discussion). It also provides channeling for thermal control of each active die such that heat signatures can be isolated.

So it becomes difficult to improve upon those coupling numbers. But I think the nano wire bonding by Vanguard offers flexibility in terms of varying architectures.

Ligentec will be at ECOC but not a finalist for any awards...their event page is very well laid out!

Lionix also uses SOI wafers as well and reports fiber coupling loss at .5dB per facet on their website.