The difficulties around wafer level testing was also discussed in some detail around the 24 minute mark.

POET has a very interesting solution that has been developed over several years. We have seen several iterations utilizing a sacrificial loopback waveguide which allows end to end testing from the send to the receive through an electrical probe. This testing takes place prior to dicing where the loopback waveguide is removed at the chip boundary. The lasers are energized by the probe and the signal is generated and measured out of plane at flip chip detectors with extremely high coupling efficiency.

You hear the panel talking about using surface  gratings which typically have poor coupling efficiency. These are also used for test points using an optical probe.  It is a very slow and time consuming approach. They are still trying to establish an efficient end to end test. POET has long since figured that one out and is protected  by patents.