This was a very good read.

February 16th, 2017 - By: Mark LaPedus

The shift from planar devices to finFETs enables chipmakers to scale their processes and devices from 16nm/14nm and beyond, but the industry faces several challenges at each node.

Cost and technical issues are the obvious challenges. In addition, cycle time—a key but less publicized part of the chip-scaling equation—also is increasing at every turn, creating more angst for chipmakers and customers alike. In fact, cost, technical hurdles and cycle time are all contributing to the ongoing slowdown of Moore’s Law.

Cycle time is the amount of time it takes to process a wafer lot in a fab from start to finish. Typically, a wafer lot consists of 25 wafers, which move through various process steps in a fab. An advanced logic process could have from 600 to 1,000 steps or more.

A simple way to look at cycle time is to apply a probability theory called Little’s Law in the fab. In this case, cycle time equals work-in-process (WIP) over the start rate, according to KLA-Tencor. For example, if a fab has 12,000 lots, and it processes 4,000 lots per month, the total cycle time is 3 months, according to KLA-Tencor.

Fig. 1: What is cycle time? Source: KLA-Tencor

It sounds simple, but it doesn’t work that way in the real world. For instance, 3D NAND and finFETs are complex 3D-like structures with more layers, as compared to their planar counterparts. It takes more steps to process them, increasing the cycle time in a fab.

To combat the increase in cycle times, chipmakers want faster equipment, with patterning tools being the top priority. In response, equipment vendors are making tools with higher throughputs. The tools can also process more advanced and smaller structures.

Despite the throughput gains, cycle times are still increasing amid the shift towards more multiple patterning steps and other processes. “Our process and product complexity have gone up faster than the productivity improvements of the tools,” said Robert Leachman, a professor of industrial engineering and operations research at the University of California at Berkeley. “Even though we’ve become much better at running factories, and the tools are much better, it takes much longer to make chips.”

Generally, the most common metric for cycle time in the fab is “days per mask layer.” On average, a fab takes 1 to 1.5 days to process a layer. The best fabs are down to 0.8 days, Leachman said.

A 28nm device has 40 to 50 mask layers. In comparison, a 14nm/10nm device has 60 layers, with 7nm expected to jump to 80 to 85. 5nm could have 100 layers. So, using today’s lithographic techniques, the cycle times are increasing from roughly 40 days at 28nm, to 60 days at 14nm/10nm, to 80 to 85 days at 7nm. 5nm may extend to 100 days using today’s techniques, without extreme ultraviolet (EUV) lithography.

To complicate matters, the cycle time in the fab increases at the start of a process, but drops as the technology matures. During the process, though, cycle times can be impacted by variability issues in the fab. The biggest hit involves the wait times between processing steps.

Fig. 2: The impact of variability on throughput and cycle times. Source: Fabtime

With those issues in mind, a chipmaker may experience a delay for a given process. The chances of a delay are greater as the complexity increases. A potential delay could increase fab costs as well as impacting time-to-market for chip customers. It’s difficult to translate that into cost, but it means lost revenue for both parties.

All told, it’s not surprising that cycle times are increasing, although conquering the problem is escalating. “The cost per memory cell or transistor is still coming down. It’s probably coming down a lot slower than it used to as we move toward the end of Moore’s Law,” Leachman said. “But the speed at which we get them is not coming down. It’s going up. That’s the big challenge. It’s worth a lot of money, and it’s a hard problem that we are not doing very well at.”

Cycle time is not limited to the fab. It’s also an issue in the photomask shop and other parts of the IC flow. All told, customers will need to get a better handle on the cycle time issues in order to have more realistic expectations about their design schedules.

Mask shop issues
The issues involving cycle time start in the photomask shop. In the flow, a chipmaker designs an IC, which is then translated into a file format. Then, a photomask is developed based on that format.

A photomask is a master template for a given IC design. After the mask is developed, it is shipped to the fab and placed in a lithography scanner. The scanner projects light through the mask, which patterns the images on a wafer.

So the mask and lithography are tied together. Today, chipmakers use 193nm wavelength lithography to print tiny features on a wafer. In reality, though, 193nm lithography reached its limit at 80nm half-pitch.

To extend 193nm lithography, chipmakers use a reticle enhancement technique (RET) called optical proximity correction (OPC). OPC makes use of tiny shapes, or sub-resolution assist features (SRAFs). The SRAFs are placed on the mask, which modifies the mask patterns to improve the printability on the wafer.

At 20nm, though, the SRAFs became too dense on the mask, making it more difficult to print discernible features on the wafer.

To solve the problem, logic vendors moved to multiple patterning. In multiple patterning, “the original mask shapes are divided between two or more masks, such that each shape has enough space around it to enable the OPC manipulations to make it printable,” explained David Abercrombie, program manager for advanced physical verification methodology at Mentor Graphics, in a blog. “Each mask is then printed separately, eventually imaging the entire set of originally-drawn shapes onto the wafer.”

Multiple patterning enables the industry to extend IC scaling, but it has some ramifications for the mask. The SRAFs are becoming smaller and more complex. “On top of that, more masks are needed due to multiple patterning,” said Aki Fujimura, chief executive of D2S. “The multiplication of each mask taking longer to produce and more masks needed creates a problem in trying to get the samples back to the customer.”

The complexity impacts the cycle time for photomask production. Instead of cycle time, mask makers use the term turnaround time (TAT), which is the time to produce and ship a mask.

In total, the TAT is about 7.28 days for a 28nm mask, according to the eBeam Initiative’s Mask Makers Survey. TATs jumped to 12.82 days for a 16nm/20nm mask, according to the survey. Though the reason for this jump was not examined in the survey, one possible theory could be the onset of multi-patterning.

TATs fell to 8.67 days for a 14nm mask, according to the survey. Though again the cause was not examined, one might speculate this to be from chipmakers gaining more experience with multi-patterning. At 10nm/7nm, though, the TAT is expected to increase to 9.52 days, according to the survey.

Fig. 3: Turnaround times are rising again Source: eBeam Initiative.

“TAT is longer due to write times, inspection times and verification times,” said Naoya Hayashi, a research fellow at Dai Nippon Printing (DNP).

Write times are the biggest culprit. As stated above, an IC design is translated into a file format. The format is translated into a set of instructions for an e-beam mask writer. This process is called mask data preparation (MDP).

Then, an e-beam mask writer takes the instructions and patterns tiny features on the mask. But as mask complexity increases, the e-beam takes longer to write them.

Fortunately, there is a solution. Recently, IMS Nanofabrication introduced a multi-beam mask writer. Equipped with 262,144 beams, the system can write an optical mask in 10 hours, compared to 30 hours for a traditional tool.

NuFlare is working on a similar system. “Multi-beam writing helps with TAT, because writing time is independent of shape count or shape complexity,” D2S’ Fujimura said.

There are other issues. “The mask shapes need to be smaller and more complex to meet the required wafer process margin, dose manipulation and the shape correction needed to achieve linearity correction,” Fujimura said. “This requires an increase in processing time for data preparation.”

D2S, for one, has developed a platform that can speed up MDP and other processes. But there are still gaps in the mask shop. The industry wants faster process control tools and other systems.

Inside in the fab
Once the mask is completed, it is transported to the fab. In a theoretical fab with 50,000 wafer starts per month, a plant may require the following equipment, according to UC Berkeley:

• 50 scanners/steppers plus wafer tracks;
• 10 high-current and 8 medium-current ion implanters;
• 40 etch machines, and
• 30 CVD tools, according to UC Berkeley.

A fab also requires cleaning systems and process control tools.

Fabs are automated plants that make use of an automated material handling system (AMHS). For this, wafers are processed and transported in an enclosed container called a front opening unified pod (FOUP). A FOUP is transported from one set of equipment to another using an overhead hoist transfer vehicle (OHT) system. The OHT travel rail can extend up to 10 kilometers with up to several hundred cars in large fabs, according to Daifuku.

Fig. 4: Unified fab transport system. Source: Daifuku

To get everything working in unison, fabs use various factory automation technologies. Vendors also use WIP flow techniques, such as real-time dispatching and scheduling, to coordinate the fab flow.

Besides the logistics, fab managers are concerned about other matters. “The manager cares about cost, cycle time and predictable yield,” said Robert Cappel, senior director of the Global Customer Organization at KLA-Tencor. The goal among chipmakers is to make reliable parts at an acceptable cost. Cycle time is also key. “Every day that I’m in a fab, it costs me more money to produce that chip,” Cappel said.

Controlling cycle time is challenging, however. For example, fab tools have certain throughput specs, which equate to a certain cycle time. “That’s how it would work in a perfect world, but there are more components in cycle time,” Cappel said. “There is the processing time. Then there is queue time, where I’m waiting to get on the tool.”

In fact, the biggest contributor to cycle times is wait times. Variability, operator delays, faulty setups and equipment downtimes are also part of the equation. In addition, fab utilization rates are also part of the mix. “If you run a fab at a very low utilization rate, you can run at raw processing times,” said Michael Lercel, director of product marketing at ASML. “But the higher utilization you run in the fab, the longer the queue time effect you have.”

And if that isn’t enough, there are other issues. “As the complexity of devices has increased, the productivity of the fab tools has decreased,” said Han Jin Lim, a technical member at Samsung Semiconductor’s R&D Center.

With that in mind, chipmakers want faster tools. But not all process steps require higher throughput tools, especially for some of the non-critical layers. “Some tools do require significant cycle time and throughput improvements,” said Prabu Raja, group vice president and general manager for the Patterning and Packaging Group at Applied Materials.

All told, cycle time is a complex issue with a multitude of variables. Here’s the formula:

Fig. 5: Cycle time components. Source: KLA-Tencor

Cycle time bottlenecks
Clearly, chipmakers hope to maintain a certain cycle time in four main fab areas—patterning, front-end-of-the-line (FEOL), backend-of-the-line (BEOL), and non-value-added operations. FEOL is where the transistor is formed in the fab, while BEOL is where the copper interconnects are made. Non-value operations include metrology and inspection.

The finFET manufacturing process starts with patterning, which is the biggest bottleneck in terms of cycle time. “As the patterning complexity increases, fab tool cycle times also increase,” Samsung’s Lim said. “It includes all steps from FEOL to BEOL.”

In today’s multi-patterning flow, chipmakers implement a two-step process—lines and cuts. First, tiny lines are patterned on a device using a technique called self-aligned double/quadruple patterning (SADP/SAQP). SADP/SAQP uses one lithography step and additional deposition and etch steps.

Fig. 6: SADP metal process where spacer is dielectric. Source: Mentor Graphics

For the cuts, chipmakers use SADP/SAQP and/or double patterning. Double patterning is sometimes called litho-etch-litho-etch (LELE). Triple patterning involves LELELE.

In multi-patterning, there are two times as many deposition, etch and clean passes or steps at 7nm, compared to 16nm/14nm. “As we go from simple single patterning, like most of 28nm to multi-patterning, the step count increases quickly,” said David Fried, chief technology officer at Coventor. “Now, an SAQP flow with three cut levels could have 60 operations, such as depositions, etches, cleans, spins and exposures.”

In the SADP flow, you pattern a layer with a resist. And then, you deposit a layer over the resist, etch back until you have deposition left on both sides of the resist line. Then, you remove the resist. SADP does not require two full litho cycles, so you’re not adding as much cycle time, according to experts.

Then, there is LELE. If you do two full litho/etch cycles to create a double pattern, then the cycle time increases. If your process has 25 litho layers, and now 5 of the layers need double patterning, you would have 30 litho cycles, according to experts.

Here’s another way to look at the problem: “For LELE double patterning, you would probably double the layer cycle time since you have to repeat the photo/etch/strip process,” Mentor’s Abercrombie said. Triple patterning increases cycle time threefold, and so on.

There are other factors as well, such as overlay and overall equipment efficiency (OEE). Overlay involves the ability of a scanner to align the various mask layers accurately on top of each other. OEE measures the work completed divided by the total time, according to UC Berkeley.

All of this adds up. “If you are doing triple patterning on some layers, and you have 50 to 60 layers, this takes a lot of time. You have all the waiting time for each of those steps. The real battle on cycle time is trying to reduce that waiting time,” UC Berkeley’s Leachman said. “One wafer doesn’t leave until all of the wafers in the lot have gone through the whole pipeline. Even though it’s one minute per wafer under the scanner, it still could be 45 minutes from when they start that lot and the robot can take the lot away.”

Any solutions?
Each chipmaker, meanwhile, has a set cycle time for a given process. It’s too difficult to specify the cycle time for each process, but clearly, cycle times are going up.

So what are the solutions? To be sure, tool vendors are making improvements. Not long ago, a 193nm scanner had throughputs of 100 wafers an hour. “Now, the scanners are 275 wafers an hour with even better precision,” ASML’s Lercel said.

It could be a different ball game if the industry adopts EUV. For example, cycle times could drop by at least a month with EUV at 7nm, he said.

Suppliers of deposition and etch tools are also making improvements. “Ultimately, it’s about the number of good die out and there are a variety of factors to consider to get good die out,” said Yang Pan, chief technology officer for the Global Products Group at Lam Research. “This includes reducing film stress during deposition, satisfying demanding requirements for finFET profiles, etching all the way down to the bottom of the feature, reducing variability, to name just a few.”

Multi-patterning also requires thin films using a slow process called atomic layer deposition (ALD). To speed up the process, some provide multi-wafer systems. “Greater utilization of the productivity benefits inherent to (multi-wafer) process architectures have proven critical for thick film deposition stacks,” Pan said.

Indeed, it requires a holistic approach. “We work with customers in simplifying the process flows used in multiple patterning, thereby reducing process steps and cost as well as reducing cycle time and process induced variation. This is enabled by using new novel films for spacers, hard masks, gapfill and highly selective etch capability,” said Uday Mitra, vice president of strategy and marketing for etch and patterning at Applied Materials.

In another approach, the industry continues to develop new cluster tools. “Right now, there are more integrated tools like deposition and etch,” Applied’s Raja said. “Now, we can put deposition and etch together, epi and etch together, and CVD and PVD together. Those kinds of integrated systems eliminate the que times.”

Another strategy is to catch the problem early. For this, chipmakers should bolster their metrology and inspection efforts. Finding a defect or detecting variability in the line can solve several problems. “Process control can help you lower your cycle time,” KLA-Tencor’s Cappel said. “The people that do the best with cycle time have a more extensive process control program in place.”

http://semiengineering.com/battling-fab-cycle-times/