Brief introduction

With the increasing demand for higher performance and more functionality in electronic devices, the expansion of traditional semiconductors is being physically constrained. Chiplet integration through advanced packaging is becoming a way to continue to drive system-level improvements, allowing different chips ("chiplets") optimized for different functions to be combined into a single package.

In this article, we will introduce the key wafer-level technologies being developed to enable high-density chiplet integration, with a focus on CEA-Leti Work in progress. We'll explore the motivations behind 3D integration, provide an overview of the processes, and explore some of the cutting-edge applications.

From traditional to advanced packages

Traditionally, packaging has been seen as a relatively simple step in encapsulating a monolithic integrated circuit chip. But over the past decade or so, packaging technology itself has become a driver of innovation, enabling entirely new system-in-package (SiP) architectures, such as the first one 3D V-cache for Apple Watch and AMD.

The morphology of a three-dimensional circuit

Three-dimensional integrated circuits consist of multiple thin semiconductor layers stacked and interconnected vertically. Key elements include:

Thin stacks with a thickness of less than 50 microns

Vertical interconnects within layers, such as through-silicon vias (TSVs) connecting the front and back sides of each layer

Vertical interconnection between layers provides high-density 3D integration

In-layer 2D interconnects using redistribution layers (RDLs).

Wafer-to-wafer bonding technology

Wafer-to-wafer bonding is one of the key processes for stacking thinned semiconductor layers. This requires thinning the chip down to 50 micron or thinner technology where they are temporarily bonded to a mechanical carrier chip and then stripped after processing.

Through-silicon via (TSV) technology

TSVs are vertically interconnected devices that pass through semiconductor chips and are used to connect stacked layers that can be used in standard CMOS Manufactured before or during the machining process. The achievable aspect ratio (depth/width) is a key metric. CEA-Leti has already demonstrated a high aspect ratio of up to 3.7 TSV and is being further expanded to achieve higher densities.

3D interconnect technology

Vertical interconnect density is a key factor, with different assembly technologies having a huge range from 10^3 to 10^8 interconnect/mm^2. At one extreme, the use of hot soldering solder micro-bump technology can be achieved as low as: A spacing of around 20 microns. At the other end of the spectrum, emerging technologies such as direct hybrid bonding enable interconnect pitches of less than 100 nanometers.

Direct hybrid bonding

Direct hybrid bonding is a key technology to achieve the highest interconnect density. Using van der Waals forces and covalent bonding forces between atomic planar semiconductors and metal surfaces, surfaces are bonded together without adding material.

The process includes specialized CMP to achieve the desired RMS of 0.5nm The following surface roughness is then bonded and annealed at room temperature to strengthen the bond. Both oxide and copper-copper bonding interfaces are available.

CEA-Leti and other companies are actively developing this process while maintaining a suitable design rulebook and a narrow process window.

Heterobonding applications

In addition to traditional logic-to-logic 3D stacking, direct hybrid bonding enables heterogeneous integration of different materials and devices. Examples of applications being studied by CEA-Leti include:

Combine μLED arrays with CMOS drivers for micro LED displays

Combines III-V devices with silicon for RF/mmWave front-end and phased array antennas

Stacking chiplets optimized for different functions (e.g., CPU, GPU, memory) onto an active silicon interposer'

CEA-Leti ecosystem

CEA-Leti An extensive ecosystem of partners has been established between industry, academia and equipment suppliers to continue to advance the development of 3D integration technology. Their backgrounds cover all challenges, from thin wafer handling, bonding process development, to system-level architecture design.

With self-driving cars, AI accelerators, and 6G With the growing demand for higher computing performance and hardware integration in applications such as communications, advanced packaging and die-to-wafer hybrid bonding will continue to be key enabling capabilities.

conclusion

Heterogeneous chiplet integration through advanced wafer-level packaging is a game-changing approach that enables semiconductors to continue to scale beyond what can be achieved with traditional monolithic process improvements alone. The technologies covered in this article, such as wafer-to-wafer bonding, high aspect ratio TSVs, micro-bump assembly, and especially direct hybrid bonding, are opening up new system architectures by combining previously separate semiconductor components into tightly integrated three-dimensional packages.

While significant challenges remain, the flexibility to flexibly mix different process nodes, materials, and optimized function blocks in a modular, interchangeable manner promises significant system-level benefits. With the major industry players and Research institutes such as CEA-Leti are driving the development of these heterogeneous integration capabilities, and we can expect more and more chiplet-based innovations to be launched on the market in the coming years.

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