Silicon-based photoelectric fusion monolithic integrated optical interconnection chip based on 45 nm CMOS process - Xunshi Optical Communication Network (iccsz.com)

A silicon-based photoelectric fusion monolithic integrated optical interconnect chip based on 45 nm CMOS process

Abstract:The team of researcher Li Ming of the Institute of Semiconductors of the Chinese Academy of Sciences and the team of researcher Qi Nan have developed the first silicon-based optoelectronic fusion monolithic integrated optical interconnection chip based on 45 nm CMOS process in China, which has successfully realized the monolithic fusion integration of optoelectronics and microelectronics

1. Job profile

With the rapid advancement of next-generation information technologies such as artificial intelligence, machine learning, and high-performance computing, the demand for broadband and energy efficiency for interconnection has increased exponentially as data migration moves. Electrical interconnects are limited by wire loss and microelectronic process evolution, which is difficult to meet the needs of ultra-high-bandwidth, 100-meter distance flat network connections in the future. Silicon-based optical interconnection technology uses the CMOS mature node process to fabricate integrated optical paths and circuits, and constructs optical input/output interfaces (optical) in the computing chip package I/O), which greatly extends the low-latency data interconnection between chips, and lays a solid foundation for building energy-efficient and massively parallel computing systems for large-capacity data transmission.

Unlike traditional network communication, computing interconnects require extremely high bandwidth density, energy efficiency, and extremely low latency, which dictates their parallel multi-channel system architectures and the need for ultra-low bit error rates (BER<10-12) without DSP assistance. However, it is worth noting that the integration of packages based on discrete optoelectronic chips not only limits the size of the chip, but also causes a significant deterioration in key performance aspects: parasitics introduced by package bonding impair signal integrity, and high-frequency signals entering and exiting the chip increase unnecessary power consumption. Silicon-based optoelectronic fusion monolithic integration technology, which integrates the design of optical devices and circuits on silicon substrates and the fabrication of a single chip, can break the inherent bottleneck of interconnection bandwidth and energy efficiency, significantly reduce packaging complexity and reduce transceiver power consumption, and is considered to be the core supporting technology to promote the sustainable development of artificial intelligence, high-performance computing and data center networks.

The team of researcher Li Ming of the Institute of Semiconductors of the Chinese Academy of Sciences and the team of researcher Qi Nan have developed the first 45 nm-based model in China The silicon-based optoelectronic fusion monolithic integrated optical interconnection chip with CMOS process has successfully realized the monolithic fusion integration of optoelectronics and microelectronics, with a single channel support64 Gb/s transmission rate, with the help of microring resonant wavelength division multiplexing technology, the total unidirectional bandwidth of 4 channels reaches 256 Gb/s。 Figure 1 shows the silicon-based photofusion monolithically integrated optical interconnect chip, which integrates optics such as microring modulators, microring filters, thermal phase shifters, and photodetectors, as well as electrical devices such as drivers and transimpedance amplifiers.

Figure 1. Silicon-based optoelectronic fusion monolithic integrated optical interconnection chip physical diagram and system block diagram.

Figure 2 is the actual picture of the chip packaging test, and Figure 3 is the large signal test results, the single-channel optical transceiver chip can achieve clear 64 Gb/s eye diagram signal transmission, and the total energy efficiency of the transceiver chip reaches 2.85 pJ/bit, the bit error rate can reach less than 10-12.

Figure 2. Actual diagram of the chip test board.

Figure 3. Eye diagram of a 4-channel transmitter and receiver with a single lane rate of 64 Gb/s NRZ.

Figure 4 shows the comparison of this work with the international representative results, where compared with the results reported in 2024 by Ayar Labs, an international leader in optoelectronic monolithic integration technology, the measured single-channel rate in this paper is 32 Gb/s to 64 Gb/s, with higher energy efficiency for transmission and receiving, provides better performance prospects for bandwidth expansion with more channels in parallel.

Figure 4. Comparison of performance with internationally relevant representative results.

The work is carried out under the "A 256 Gb/s Electronic-Photonic Monolithically Integrated Transceiver in 45 nm CMOS", a short communication paper was published in the Journal of Semiconductor, and the results and progress were quickly reported.

This work was supported by the National Natural Science Foundation of China: the National Fund for Distinguished Young Scholars (61925505), the Major Research Program for the Scientific Foundation of Frontier Technology of Integrated Chips (92373209), and the Key Fund (62235017).

About the author: Li Ang is currently pursuing a Ph.D. in semiconductor research at the Chinese Academy of Sciences. At present, his main research direction is high-speed optoelectronic devices and optoelectronic integration of silicon photonics.