"The requirement that NAND controllers manage bad blocks and spread writes throughout the NAND also requires that the physical block locations where data is actually written to the NAND differ from the logical block locations seen by a file system. This logical-to-physical mapping must be maintained by the software and imposes not only additional memory requirements for data structures but also added processor cycles for their maintenance. These requirements scale proportionally to the size of the attached NAND device or devices used."

Not a problem for e.Digital, no additional memory requirements necessary, for MLC or SLC NAND. While beating that, with yet, other bells and whistles allowing for non contiguous or contiguous total data recall under complex utility.

We wait

doni