"Therefore, assuming that SAMSUNG and its 12 engineers who left it to form a side company that for years were THIS CLOSE ,(cross your index finger with the one next to it), learned something from EDIG which gave them the idea of producing FLASH chips in such a manner that will permit the "Gate keeping" which MOS was/is allegedly doing through software control of data dissimination."

I have no idea if there was a collaboration for the effort. Simple contiguous arrangements where available.

I'm only considering what I know.

What I know:

1. NOR....was the fist memory characteristics available to e.Digital, featuring cross point architecture(row and column) for addressing....or parallel memory....as I see it, e.Digital formats it's IP and utilizes the ROW only.

2. NAND....came later featuring serial architecture (row only) for addressing. e.Digitals IP is devised for the attributes of row only or serial memory. Other manners are available to drive a serial array...ie: simple contiguous arrangements. Serial memory is easier to produce.

E.Digital developments are specific to serial memory or NAND, with that, the developments are commanding(contiguous and non contiguous) and on par with the status quo abilities of parallel architectures. That non contigious ability is very important.

WE followed the NOR vs NAND battles and are aware of the winners. I place more value with regard to e.Digital and the out come of battle, than what you consider above, as there were simple methods to format. It took something of significance to out pace the ability of NOR. It was the reason I followed the battle, and the reason I'm still here.

In prior posts, I'm trying to convey to you, that we are not involved in IP development for physical hardware. Transistor gates are physical developments.

We can control the gates of both NOR and NAND....or any memory characteristics under the same format for any......nonvolatile or volatile memory.

all it takes is tweaking

doni