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Message: Arrogant form letter from Agoracom with no details.

Some times ago there was a discussion in this board that DUANE MORRIS accepted the contingency plan just for sake of money . But contrary when we looked in few articles that has been written it was disclosed they only accept an IP case when in depth due dilligence done and finally presented to team of expert inside and (outside contractor) lawyer and finally they take the responsibility of the case .Here is another FLASH MEMORY patent that DUANE MORRIS representing their agent and firm.



US Patent 6878986 - Embedded flash memory cell having improved programming and erasing efficiency

US Patent Issued on April 12, 2005
Estimated Patent Expiration Date: March 31, 2023

Inventors





Assignee





Application

No. 10403137 filed on 03/31/2003



US Classes:

257/315, With floating gate electrode257/E21.682, With source and drain on same level and without cell select transistor (EPO)257/E27.103, Electrically programmable ROM (EPO)438/265, Oxidizing sidewall of gate electrode438/279, Making plural insulated gate field effect transistors having common active region438/283, Plural gate electrodes (e.g., dual gate, etc.)438/303Utilizing gate sidewall structure



Field of Search

257/E21.682, With source and drain on same level and without cell select transistor (EPO)257/E27.103, Electrically programmable ROM (EPO)438/265, Oxidizing sidewall of gate electrode438/279, Making plural insulated gate field effect transistors having common active region438/283, Plural gate electrodes (e.g., dual gate, etc.)438/303Utilizing gate sidewall structure



Examiners

Primary: Nelms, David C.
Assistant: Tran, Mai-Huong




Attorney, Agent or Firm





US Patent References

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Inventor: Hong
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Inventor: Hsieh, et al.
6074914, Integration method for sidewall split gate flash transistor
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Inventor: Ogura
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Inventor: Wang
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Issued on: 03/27/2001
Inventor: Wang
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Inventor: Liou, et al.
6355524, Nonvolatile memory structures and fabrication methods
Issued on: 03/12/2002
Inventor: Tuan, et al.
6355527, Method to increase coupling ratio of source to floating gate in split-gate flash
Issued on: 03/12/2002
Inventor: Lin, et al.
6380583, Method to increase coupling ratio of source to floating gate in split-gate flash
Issued on: 04/30/2002
Inventor: Hsieh, et al.
6384450, Semiconductor memory device and method of manufacturing the same
Issued on: 05/07/2002
Inventor: Hidaka, et al.
6414350, EPROM cell having a gate structure with dual side-wall spacers of differential composition
Issued on: 07/02/2002
Inventor: Hsieh, et al.
6432773, Memory cell having an ONO film with an ONO sidewall and method of fabricating same
Issued on: 08/13/2002
Inventor: Gerber, et al.
6479346, Semiconductor memory device and fabrication method thereof
Issued on: 11/12/2002
Inventor: Yi, et al.
6479859, Split gate flash memory with multiple self-alignments
Issued on: 11/12/2002
Inventor: Hsieh, et al.
6482699Method for forming self-aligned contacts and local interconnects using decoupled local interconnect process
Issued on: 11/19/2002
Inventor: Hu, et al.




International Class

H01L029/788
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