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Message: PACER- EDIG's Opening Claim Construction Brief

re: 296 p. 40

"Now, with respect to the present limitation, Defendants make a more direct attack by attempting to read into claims 1 and 19 the negative limitation “without another memory system such as RAM.” In other words, Defendants are taking two bites at the same apple (i.e., (1) circuitously arguing that flash memory is main memory and therefore a replacement for RAM memory, and (2) arguing RAM is precluded from being in the system) with the hope that the Court will adopt at least one of their constructions so that Defendants can later try to create a non-infringement position to the extent any of the accused devices have RAM. However, just as Defendants’ proposed construction for flash memory is flawed, their proposed construction for “sole memory of the received processed sound electrical signals” likewise is flawed. "

All the magic is in e.Digitals high speed I/O controller considerations.....e.Digital eliminates a majority of RAM resource, however, the high speed cache is sized to a minimum of one read /write block attribute of the flash memory. You can't eliminate all of the RAM.

The cache is a page through element that does not have to deal with directive structures ....ie FAT for data management issues.

I can't imagine a judge allowing them to get away with what they are pushing.

e.Digital "emulates" RAM resource, but they don't eliminate it totally.

doni

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