Might this help to discredit the allegations of Shaw and Hamilton(note the time-frame): 

"You look this up you will see that INTEL has openly used variable speed clocking on their processors. funny they never claimed to have invented it . or patent it. Then suddenly in 1999 they developed what they call speed step. which is the same basic thing. and they say they developed this . no claim of a patent to protect this key fundamental processing that is the heart of all their processors.

we know why. and they do also. PTSC had a patent pending on this tech. for years it got held up for ever in legal battles and the patent office dragging their feet.

I don't think Intel ever thought that ptsc would ever get this patent awarded to them.

Intel has been sued many times before for infringement and has lost in court and also settled cases, out of court.

How about someone doing a little homework on patents and see what intel holds. all these big company's love to steal tech. microsoft is the biggest thief.

Funny indeed, Intel cannot patent it because it already belongs to Patriot Scientific # 5,809,336, otherwise...you know they would have. Hell, I think the only entities that have more patents are IBM and GOD. So, I decided to take elkman1310's advice and look it up for myself.
Due Diligence; when searching for information I almost always hit a dead end, but every so often I come across a find that makes it all worth while. I ran a search on the very title of PTSC's patent 5,809,336 "High Performance Microprocessor Having Variable Speed System Clock."

Low and behold, among the returns were a couple of very old sites (1996 - one year after PTSC filled for patent 5,809,336) by ARM (Advanced RISC Machines Ltd) and Digital Semiconductor -- development collaborators of Intel (among many others). In the text it goes on to describe features and functions of this NEW Intel StrongARM SA-110 Microprocessor, the FIRST member of the StrongARM family of high performance, low power microprocessors, the very foundation in which most of their microprocessors are built today. (registered trademarked - NOT patented)

When I first read this information, after I had read PTSC's patent, I swear, it gave me goosebumps -- the best goosebumps I've ever had. There are many notable correlation's, one I particularly like is: excerpt from Intel StrongARM SA 110 Datasheet 1996 --"Clocks --The SA-110 receives 3.68-MHz clock from a crystal based clock generator. The SA-110 uses an internal phase-locked loop (PLL) to multiply the frequency by a veriable multiplier to produce a high speed clock. The high speed clock is then divided internally by a configureable ratio to provide a system clock for synchronous operation. The 3.68MHz oscillator and PLL run constantly in normal and idle mode." Note -- the header for "Clocks" is plural and the clock is "divided" to create a second clock for synchronous operation. Excerpts from PTSC's U.S. Patent 5,809,336 1995 --"A high performance, low cost microprocessor system having a variable speed system clock is disclosed herein. The microprocessor system includes an integrated circuit having a central processing unit and a ring oscillator variable speed system clock for clocking the microprocessor. The central processing unit and ring oscillator variable speed system clock each include a plurality of electronic devices of like type, which allows the central processing unit to operate at a variable processing frequency dependent upon a variable speed of the ring oscillator variable speed system clock. The microprocessor system may also include an input/output interface connected to exchange coupling control signals, address and data with the central processing unit. The input/output interface is independently clocked by a second clock connected thereto." & "Most microprocessors derive all system timing from a single clock. The disadvantage is that different parts of the system can slow all operations. The microprocessor 50 provides a dual-clock scheme as shown in FIG. 17, with the CPU 70 operating a synchronously to I/O interface 432 forming part of memory controller 118 (FIG. 2) and the I/O interface 432 operating synchronously with the external world of memory and I/O devices. The CPU 70 executes at the fastest speed possible using the adaptive ring counter clock 430. Speed may vary by a factor of four depending upon temperature, voltage, and process. The external world must be synchronized to the microprocessor 50 for operations such as video display updating and disc drive reading and writing. This synchronization is performed by the I/O interface 432, speed of which is controlled by a conventional crystal clock 434
Excerpt from Intel/ARM/Digital SA-110 Datasheet -- "The Digital Semiconductor 110-SA microprocessor (SA-110) is the first member of the StrongARM family of high-performance, low power microprocessors. The SA-110 is the latest implementation of advanced RISC Machines Ltd. (ARM) Version 4 architecture and offers significant advances in microprocessor design. The SA-110 has been designed to further extend the ARM family as the worlds leading source of low power, high performance RISC processors for embedded consumer markets such as smart hand held devices and interactive digital video. The SA-110 is a general purpose, 32-bit microprocessor with a 16KB instruction cache (Icache); a 16KB, write-back data cache (Dcache); a write buffer; and a memory management unit (MMU) combined in a single chip"

Excerpt PTSC Patent -- "DETAILED DESCRIPTION OF THE INVENTION

Overview

The microprocessor of this invention is desirably implemented as a 32-bit microprocessor optimized for:

HIGH EXECUTION SPEED, and

LOW SYSTEM COST.

In this embodiment, the microprocessor can be thought of as 20 MIPS (million instructions per second)
for 20 dollars. Important distinguishing features of the microprocessor are:

Uses low-cost commodity DYNAMIC RAMS to run 20 MIPS

4 instruction fetch per memory cycle

On-chip fast page-mode memory management

Runs fast without external cache

Requires few interfacing chips

Crams 32-bit CPU in 44 pin SOJ package

The instruction set is organized so that most operations can be specified with 8-bit instructions. Two positive products of this philosophy are:

Programs are smaller,

Programs can execute much faster.

The bottleneck in most computer systems is the memory bus. The bus is used to fetch instructions and fetch and store data. The ability to fetch four instructions in a single memory bus cycle significantly increases the bus availability to handle data.



...Another excerpt
of great interest --"More recently, it has been perceived that performance gains can be achieved through comparative simplicity, both in the microprocessor integrated circuit itself and in its instruction set. This second approach provides RISC microprocessors, and is exemplified by the Sun SPARC and the Intel 8960 microprocessors. However, even with this approach as conventionally practiced, the packages for the microprocessor are large, in order to accommodate the large number of pinouts that continue to be employed. A need therefore remains for further simplification of high performance microprocessors."

Dec 6, 1999 -- "Intel is preparing a variable clock-speed technology it calls SpeedStep"
http://www.mdronline.com/mpr_public/editorials/edit13_16.html

December 15, 1999 -- "According to Intel, this delivers the best of both worlds: low power in battery mode, near-desktop performance when plugged in. AMD plans to deliver its own variable-speed technology, known as Gemini, in 1H00" -- http://www.mdronline.com/publications/mpw/issues/mpw029.html "

Be well