Yes, very helpful. I had to read it a couple of times, and not until I absorbed the document from the perspective of defendants claim construction, was I able to see where we look to be good:

From the Markman: 

The defendants propose sets of from 1 to a maximum number of sequential instructions, in which the execution of the instruction depends on each set being provided to the instruction register as a unit and in which any operand that is present must be right justified and which cannot encompass a single 32-bit traditional conventional instruction. 

From the USPTO review:

Since Sachs decodes the instruction in the central processing unit, Sachs cannot perform the step of "supplying, from said instruction groups, using the predetermined location, said operand or instruction or both to said central processing unit," as required by claim 29 because the decoding must be done prior to delivering the instruction or operand to the central processing unit and in Sachs the decoding is done in the central processing unit. Sachs clearly teaches that instructions from the line register 400 are not decoded until after they are separated into words, supplied via a bus to the CPU, and separated further into half-words that pass through several prefetch registers before reaching an instruction decoder.

Based on my hurried interpretation (I am currently being harrased to get off the PC and get on the road to go see the family..LOL), I have to believe that because according to Sachs the decoding is done in the CPU, ARM's claim doesn't make sense. Yes, in your words, there is a lot to chew..LOL..so I plan to bring this doc with me and read it whenever I can hide...between football games of course. But, in a nutshell....I think you may be correct!

Good luck to you, me, us, and all longs.

Happy Thanksgiving everyone!