Note: Sh-Boom is comprised of two CPU`s the main CPU 70 and a DMA CPU....with memory controller 118...etc

The designer of a high speed microprocessor must produce a product which operate over wide temperature ranges, wide voltage swings, and wide variations in semiconductor processing.

Temperature, voltage, and process...all affect transistor propagation delays. Traditional CPU designs are done so that with the worst case of the three parameters, the circuit will function at the rated clock speed. The results are designs that must be clocked a factor of two slower than their maximum theoretical performance, so they will operate properly in worse case conditions.

The micro processor 50(ShBoom) uses the technique shown in FIGS 17-19 to generate the system clock and its required phases.

Clock circuit 430 is the familiar ``ring-ocillator`` used to test process performance. The clock is fabricated on the same silicon chip as the rest of the microprocessor 50(Sh-Boom).

The ring oscillator frequency is determined by the parameters of temperature, voltage, and process. At room temperature, the frequency will be in the neighborhood of 100 MHZ. At 70 degrees Centigrade, the speed will be 50 MHZ.

The ring oscillator 430 is useful as a system clock,

with its stages 431(part of the clock scheme) producing phase 0-phase 3 outputs 434(I/O of the clock scheme) shown in FIG. 19, because its performance tracks the parameters which similarly affect all other transistors on the

same silicon die.

By deriving system timing from the ring oscillator 430, CPU 70(main CPU) will always execute at the maximum frequency possible, not never too fast. For example, if the processing of a particular die is not good resulting in slow transistors, the latches and gates on the croprocessor 50 will operate slower than normal. Since the microprocessor 50 ring oscillator clock 430 is made from the same transistors on the same die as the latches and gates, it too will will operate slower (oscillating it at lower frequency), providing compensation which allows the rest of the chip`s logic to operate properly.

ASYNCHRONOUS/SYNCHRONOUS CPU....

Most microprocessors derive all system timing from a single clock(external crystal). The disadvantage is that different parts of the system can slow all operations.

The microprocessor 50 provides a dual-clock scheme as shown in FIG 17, with the CPU 70(main CPU) operating a synchronously to I/0 interface 432 forming part of memory controller 118 Fig 2 and the I/0 interface 432 operating synchronously with the external world of memory and I/0 devices.

The CPU 70 executes at the fastest speed possible using the adaptive ring counter clock 430. Speed may vary by a factor of four depending upon temperature, voltage,and process.

The external world(32 bit external bus to memory array) must be synchronized to the microprocessor 50(Sh-Boom) for operations such as video display updating and disk drive reading and writing. This synchronization is performed by the I/0 interface 432, speed of which is controlled by a conventional crystal clock 434.

The interface 432 processes requests for memory accesses from the microprocessor 50 and acknowledges the presence of I/O data.

The microprocessor 50 fetches up to four instructions in a single memory cycle and can perform much useful work before requiring another memory access.

By decoupling the variable speed of the CPU 70 from the fixed speed(Crystal clock) of the I/O interface 432, optimum performance can be achieved by each. Recouplin-Recoupling(the clocks) between the CPU 70 and the interface 432 is accomplished with handshake signals on lines 436, with data/address passing on bus 90, 136.

ASYNCHRONOUS/SYNCHRONOUS CPU imbedded on a DRAM chip...

This is a processor with a combination of DRAM 311/ and CPU 314 mated on the same substraight. It`s not the Sh-Boom processor as it utilizes different techniques within

that double the speed of the Sh-Boom...it does not utilize the same register and fetch array as on the Sh_Boom....it does not have a name...and more than likely morphed into the Ignite.

This processor has direct memory access to the DRAM without an external bus and does not need the external clock necessary for the Sh-Boom processor...with regard to memory management.

That highlight above is why Intel would want the patent problem cleaned up...when they design and final a run...they have to clock it down for

customer satisfaction and quality....with the Fish clock they would have an ability to utilize the max speed without penalty.....this for speed...a degree of simplification..and satification of the customer.

It`s a quality control issue...as well as speed....the material I posted of Intel Arm...IMO is utilizing this methodology.

doni