After further digging, now I am more inclined to believe the 749 patent is more of a threat, not to ARM's past, but to its future. Interesting that ARM only now is contesting the 749. You need to look at the most recent announcements regading their Cortex processors. They are superscalar architecture. That is different from the past. If you read up on the architecture you will see that there are two phrases that might conflict with the 749. Parallel instruction fething and the bus bandwith to handle it. I believe these are the key terms in the 749 that are threatening ARM. Here is claim one again with the pertinent sections underlined. All IMHO and I really do not know this stuff, so take it for what its worth. Opty

1. A microprocessor system, comprising a central processing unit integrated circuit, a memory extend of said central processing unit integrated circuit, a bus connecting said central processing unit integrated circuit to said memory, and means connected to said bus for fetching instructions for said central processing unit integrated circuit on said bus from said memory, said means for fetching instructions being configured and connected to fetch multiple sequential instructions from said memory in parallel and supply the multiple sequential instructions to said central processing unit integrated circuit during a single memory cycle, said bus having a width at least equal to a number of bits in each of the instructions times a number of the instructions fetched in parallel, said central processing unit including an arithmetic logic unit and a first push down stack connected to said arithmetic, logic unit, said first push down stack including means for storing a top item connected to a first input of said arithmetic logic unit to provide the top item to the first input and means for storing a next item connected to a second input of said arithmetic logic unit to provide the next item to the second input, a remainder of said first push down stack being connected to said means for storing a next item to receive the next item from said means for storing a next item when pushed down in said push down stack said arithmetic logic unit having an output connected to said means for storing a top item.