From Albie:

My Brief Break down of brief Arguments that will impact the decision of the USPTO:

From Page 16 USPTO Arguments:

The Patent Owner would like to thank Examiner Banankhah for the courtesies extended in the interview on September 13, 2007 at the USPTO. The interview was attended by Examiner Banankhah, two Conferee Examiners, the inventor Charles H. Moore ("the inventor"), and the undersigned attorney of record Larry Henneman ("the attorney of record"). During the interview, the inventor and the attorney of record explained aspects of the invention and then presented reasons why the invention was distinguishable over the cited references. Because there are eleven references and only a limited amount of time to conduct the interview, all eleven references were not individually discussed. Instead, particular distinctions that exist with respect to several of the references were presented, using only a few of the references as examples. Nevertheless, one or more of the distinctions presented in the interview apply to each of the eleven references. Although no agreement was reached during the interview with respect to any particular reference, that was not the Patent Owner's purpose for the interview. My comment: No need to be alarmed they are not supposed to be there to persuade the examiner, only to assist in clarifications

From Page 17 USPTO Arguments:

"A claim is anticipated only if each and every element as set forth in the claim is found, either expressly or inherently described, in a single prior art reference." Verdegaal Bros. v. Union Oil Co. of California, 2 USPQ2d 1051, 1053 (Fed. Cir. 1987). "The identical invention must be shown in as complete detail as is contained in the ... claim." Richardson v. Suzuki Motor Co., 9 USPQ2d 1913, 1920 (Fed. Cir. 1989).

The Patent Owner respectfully submits that claim 29 is patentable over each and every one these references. Claim 29 recites:

29. In a microprocessor system including a central processing unit, memory, and an instruction register, a method for providing instructions and operands from said memory to said central processing unit comprising the steps of:providing instruction groups to said instruction register from said memory wherein certain of said instruction groups include at least one instruction that, when executed, causes an access to an operand or an instruction or both, said operand or instruction being located at a predetermined position from a boundary of said instruction groups; decoding said at least one instruction to determine said predetermined position;locating said predetermined position; and supplying, from said instruction groups, using the predetermined location, said operand or instruction or both to said central processing unit. The Patent Owner submits that none of the references, either expressly or inherently, teach each and every element of claim 29.CLAIM REJECTION UNDER 35 U.S.C. § 102(B) USING POMERENE (U.S. PAT NO. 4,295,193).Claim 29 was rejected under 35 USC 102(b), as being anticipated by "Pomerene" (U.S. Pat. No. 4,295,193). The reasons used in the Office Action for rejecting claim 29 under Pomerene were adopted from the Request for Ex Parte Reexamination filed by Michael Hawes on behalf of Toshiba Corp. on October 19, 2006 ("the Request for Ex Parte Reexamination"). In order for Pomerene to anticipate claim 29, Pomerene must either expressly or inherently teach each and every element set forth in claim 29. The Patent Owner submits that Pomerene does not expressly or inherently teach each and every element of claim 29.Pomerene does not disclose "decoding said at least one instruction to determine said predetermined position."

From Page 19 USPTO Arguments:

Pomerene does not disclose "decoding said at least one instruction to determine said predetermined position," as recited in Claim 29. The Office Action asserts that "decoding of any branch or jump instruction to a non type 1 instruction determines that the instruction is at a predetermined left boundary of the instruction group." The Patent Owner respectfully disagrees, because Pomerene discloses that the position of a branch target within a multi-instruction word is determined by reading address bits, not by decoding the branch instruction. From Page 20 USPTO Arguments: Clearly, Pomerene is reading address bits (i.e. "1011 ") to determine the branch location and not decoding an instruction. Indeed, Pomerene expressly states that the high order bits are used to "address" the multi-instruction words and the low order bits are used to indicate where "the instruction sequence is to begin." Furthermore, Pomerene expressly states that the bits are "necessary" to address the multi-instructions words. There is absolutely no indication in Pomerene that the target location is determined by decoding the branch instruction. For at least these reasons, the Patent Owner respectfully asserts that Pomerene fails to disclose "decoding said at least one instruction to determine said predetermined position," as recited in the claim. B. Pomerene does not disclose "providing instruction groups to said instructionregister ... said operand or instruction being located at a predetermined position from a boundary of said instruction groups. "Pomerene does not disclose an instruction that accesses an "operand or instruction being located at a predetermined position from a boundary of said instruction groups," as recited in Claim 29. Rather, as indicated above, Pomerene uses address bits to access instructions. The Office Action asserts (in part) that:any branch or jump instruction that addresses a non "type one" instruction causes an access to an instruction at a predetermined position from the boundary of an instruction group because the non "type one" instruction is always at the left boundary of an instruction group. In addition, the microprocessor of Pomerene teaches that memory fetches are aligned at instruction group boundaries of 4 words. In one example shown in Figure 3, the arrow 70 indicates a branch from the instruction at 1011 to the instruction at 0101. Pomerene teaches that the branch is accomplished by supplying only the high order bits "01 " to the instruction cache which supplies the entire instruction group containing the instruction at 0101 to the instruction register 10. Col. 6,11. 9-40. This access is always at a 4 instruction group boundary.

From Page 21 USPTO Arguments:

The Office Action asserts that "Pomerene teaches that the branch is accomplished by supplying only the high order bits "Ol." However, the high order bits only serve to locate the multi-instruction word. The lower order bits are necessary to identify the branch target, which is a particular instruction within the group.The portion of Pomerene cited by the Examiner discloses that the address of a branch target (e.g., instruction 5 in FIG. 3) is provided with a branch instruction (e.g., instruction 11 in FIG. 3). The target address includes high-order bits ("O1" in this example) that identify a multiinstruction word that contains the target as well as low-order bits (also "O1" in this example) that identify the address of the target within the multi-instruction word. These designations are merely addresses within the multi-instruction word. Therefore, as shown in FIG. 3, the target instruction can be any instruction, regardless of the position of that instruction relative to the boundary of a multi-instruction word. Since the target instruction can be any instruction within the multi-instruction word, the target instruction is not located at a predetermined position from a boundary of said instruction groups, as recited in claim 29. The Office Action also points out that the branch target could be a non type-one instruction in which case the target would necessarily be in the first position. This is true but irrelevant. Pomerene does not teach a "branch to non-type-one" instruction or that the branch instruction has any features specific to the case where the target happens to be the first instruction in a multi-instruction word. In the absence of information to the contrary, one skilled in the art would infer that branching to a non-type-one instruction is handled by providing the

From Page 22 USPTO Arguments:

low order address bits (which would be "00" in this case) to the circuits that control delivery of instructions to the processing circuits, exactly as Pomerene describes. In fact, Pomerene specifically states that these non "one type" instructions are "executed therein in the normal manner." (Pomerene, col. 4, lines 61-62). Therefore, no special handling of non-type one instructions as branch targets is even suggested by Pomerene. In any case, in order to anticipate Claim 29, the reference must disclose each and every limitation as recited in the claim, which it does not.C. Pomerene does not disclose a method "/iln a microprocessor system."Claim 29 recites (in part) a method "[i]n a microprocessor system." Pomerene does not disclose a microprocessor system as recited in Claim 29. Rather, Pomerene discloses a main frame computer system. Therefore, Pomerene does not anticipate Claim 29.Indeed, the rejection of Claim 29 does not even assert that Pomerene discloses a microprocessor system. The Office Action asserts: "Pomerene teaches a computing machine with a central processing unit (Fig. 40), an instruction register (10 of Fig. 1) memory (Fig. 3). Pomerene teaches a method for providing instructions and operands from said memory to said central processing unit." However, Pomerene does not disclose a microprocessor system, and there is no indication in Pomerene that the disclosed method is suitable for use in a microprocessor system. Although Pomerene may teach a central processing unit (Fig. 40), an instruction register (10 of FIG. 1) and a memory (Fig. 3), Pomerene discloses these elements in a main frame computer system, which is completely different and not applicable to the claimed invention. Specifically, Pomerene's main frame computer system includes multiple instruction execution machines. In column 3 lines 27-29, Pomerene describes his machines as "FIGS. 1 A and 1 B are a block diagram representation of the multiple instruction execution machine[s] according to the present invention." Pomerene's figures lA and IB are provided below to illustrate that Pomerene is not directed to microprocessors but instead at large computing machines. Therefore, Pomerene does not disclose this element of claim 29.

From Page 23 USPTO Arguments:

Further exemplary evidence that Pomerene's disclosure relates to main frame computers rather than microprocessor systems is that Pomerene uses "cables" to connect the different components within the main frame computer. Clearly, components of a microprocessor system are not connected together by cables. In addition, the Examiner is respectfully reminded that main frame computers today are significantly different than the main frame computers that existed at the time of the present invention

Page 24 USPTO Arguments:

one of ordinary skill in the art would confuse a main frame computer with a microprocessor system, either now or at the time of the present invention.For at least the reasons set forth above, the Patent Owner respectfully asserts that the concept of a "microprocessor system" is non-existent in the Pomerene reference. Therefore, Pomerene does not anticipate claim 29.D. Pomerene does not disclose "locating said predetermined position; and supplyinj!, from said instruction zroups, usinz the predetermined location, said operand or instruction or both to said central processing unit.'The Patent Owner submits that because Pomerene fails to disclose the use of any "predetermined position," Pomerene cannot disclose "using the predetermined location" to supply an instruction to the central processing unit. Therefore, Pomerene does not anticipate Claim 29, for this reason as well. E. ConclusionFor at least the foregoing reasons, Claim 29 is not anticipated by Pomerene, because Pomerene does not disclose each and every element of Claim 29. In particular, Pomerene does not disclose "decoding said at least one instruction to determine said predetermined position." Pomerene also does not disclose an instruction that accesses an "operand or instruction being located at a predetermined position from a boundary of said instruction groups." In addition, Pomerene does not disclose a method in "a microprocessor system." Yet further, Pomerene does not disclose "locating said predetermined position" and "using the predetermined location" to supply an instruction to the central processing unit. Each of these limitations is expressly recited in Claim 29. Therefore, the Patent Owner respectfully requests that, in light of these remarks, the 35 U.S.C. § 102 rejection of Claim 29 based on Pomerene be withdrawn. My friends this is why the J’s Caved in Page 26 the nail through the heart of the vampire patent thieves! The Patent Owner respectfully disagrees because Sachs fails to disclose an "instructionregister," as recited in claim 29. Sachs fails to disclose an "instruction register" for at least two reasons, explained in detail below. 1) Sachs fails to disclose an "instruction register," as the term is construed according to the Patent Owner's construction, which has been adopted by the Office Action.

Sachs fails to disclose an "instruction register," as the term is construed according to the Patent Owner's construction, which has been adopted by the Office Action.

In the concurrent litigation involving the present patent, Technology Properties LTD. and Patriot Scientific CORP. v. Matsushita Electric Industrial Co., LTD, et al, Civil Action No. 2:05-CV-494 (TJW) ("Concurrent Litigation"), the Patent Owner construed the term "instruction register" as follows:a hardware element that receives and holds an instruction group as it is extracted from memory, the register either contains or is connected to circuits that interpret the instructions in the group.This construction was adopted by the Office Action. See Office Action at page 3: ("The Patent Owner has admitted in litigation definitions for the claim terms of the '584 patent in the 'Texas Litigation'. As such, the Examiner concurs with the patent owner's claim construction in that litigation...")Under this construction, Sachs fails to disclose an "instruction register." The Office Action has pointed to Sachs' line register 400 in FIG. 14 as allegedly being an instruction register. However, Sachs' line register 400 does not contain and is not connected to circuits that interpret instructions in the group. This is clearly shown in FIG. 14 of Sachs which is reproduced below:

The construction advanced by the Patent Owner was agreed to by the opposing party and ultimately adopted by the Court in the Concurrent Litigation. See Markman Ruling: Memorandum Opinion and Order at page 8, Technology Properties LTD. and Patriot Scientific CORP. v. Matsushita Electric Industrial Co., LTD, et al., Civil Action No. 2:05-CV-494 (TJW), (E.D. Tex. June 15, 2007), Document 259.

My IMO:

Its funny that the J's coincidently agreed for the 30 motion to stay around the same time frame as this arguments were released, this is the stake that was driven through thier Vampiring Patent stealing heart !

The rest of the 89 pages are a sheer empitamy of excellence by the attornies for the MMP, they argued quite tactfully and I can see a spirit of excellence, they proved how the J's (and Pubpat) where trying to confuse the patent office!

Im buying more!!!

http://agoracom.com/ir/patriot/forum...

Be well