So, since he's either too intellectually dishonest to respond, or simply ignorant of the facts, I'll simpy post the information.

Here's are the two versions of claim 29 as posted in the Notice of Intent to Issue Reexam Certificate first and in today's Official Gazette. The first version of each is showing the deleted words removed, and the new words inserted so that it reads just as it should without having to stumble over the additions and subtractions. The second version of each shows how they appeared in each document. I've added green coloring to the words added and red coloring to the words deleted for visual clarity. As you can see they are the same. Why milestone wants to mislead, is an interesting question, but for someone who accuses others of FUD, it appears he enjoys participating in it at times.

Notice of Intent Version:

Claim 29. (amended) In a microprocessor system including a central processing unit, memory, and an instruction register, a method for providing instructions and literal operands from said memory to said central processing unit comprising of the steps of:

Providing instruction groups to said instruction register from said memory;

wherein said instruction register is connected to circuits that decode instructions; wherein each of said instruction groups is structured to comprise a set of locations, including a first location, that contain either instructions or operands or both, said operands comprising either literal operands or variable-length address operands, and said instructions including opcode bits or both opcode bits and address selection bits but not including variable-length address operands; and further

wherein certain of said instruction groups include at least one instruction that, when executed, causes an access to an instruction, or to a literal operand and an instruction, said accessed literal operand or said accessed instruction being located at a predetermined position from a boundary of said instruction groups, said accessed instruction positioned at only the first location of an instruction group;

decoding said at least one instruction group to determine at least said predetermined position of said accessed instruction as only the first location of the set of locations of the instruction group containing said accessed instruction;

locating at least said predetermined position; and

supplying said accessed instruction, or said accessed literal operand and said accessed instruction, from said instruction groups to said central processing unit, using at least said predetermined position.

Official Gazette Version:

29. In a microprocessor system including a central processing unit, memory, and an instruction register, a method for providing instructions and literal operands from said memory to said central processing unit comprising the steps of:

providing instruction groups to said instruction register from said memory;

wherein said instruction register is connected to circuits that decode instructions;

wherein each of said instruction groups is structured to comprise a set of locations, including a first location, that contain either instructions or operands or both, said operands comprising either literal operands or variable-length address operands, and said instructions including opcode bits or both opcode bits and address selection bits but not including variable-length address operands; and further

wherein certain of said instruction groups include at least one instruction that, when executed, causes an access to an instruction, or to a literal operand and an instruction, said accessed literal operand or said accessed instruction being located at a predetermined position from a boundary of said instruction groups, said accessed instruction positioned at only the first location of an instruction group;

decoding said at least one instruction to determine at least said predetermined position of said accessed instruction as only the first location of the set of locations of the instruction group containing said accessed instruction;

locating at least said predetermined position; and

supplying said accessed instruction, or said accessed literal operand and said accessed instruction, from said instruction groups to said central processing unit, using at least said predetermined position.

Notice of Intent Version:

Claim 29. (amended) In a microprocessor system including a central processing unit, memory, and an instruction register, a method for providing instructions and literal operands from said memory to said central processing unit comprising of the steps of:

Providing instruction groups to said instruction register from said [memory]

memory;

wherein said instruction register is connected to circuits that decode instructions; wherein each of said instruction groups is structured to comprise a set of locations, including a first location, that contain either instructions or operands or both, said operands comprising either literal operands or variable-length address operands, and said instructions including opcode bits or both opcode bits and address selection bits but not including variable-length address operands; and further

wherein certain of said instruction groups include at least one instruction that, when executed, causes an access to an instruction, or to a literal operand [or] and an instruction [or both], said accessed literal operand or said accessed instruction being located at a predetermined position from a boundary of said instruction groups, said accessed instruction positioned at only the first location of an instruction group;

decoding said at least one instruction group to determine at least said predetermined position of said accessed instruction as only the first location of the set of locations of the instruction group containing said accessed instruction;

locating at least said predetermined position; and

supplying said accessed instruction, or said accessed literal operand and said accessed instruction, from said instruction groups to said central processing unit, using [the] at least said predetermined position [location, said operand or instruction or both to said central processing unit].

Official Gazette Version:

29. In a microprocessor system including a central processing unit, memory, and an instruction register, a method for providing instructions and literal operands from said memory to said central processing unit comprising the steps of:

providing instruction groups to said instruction register from said memory;

wherein said instruction register is connected to circuits that decode instructions;

wherein each of said instruction groups is structured to comprise a set of locations, including a first location, that contain either instructions or operands or both, said operands comprising either literal operands or variable-length address operands, and said instructions including opcode bits or both opcode bits and address selection bits but not including variable-length address operands; and further

wherein certain of said instruction groups include at least one instruction that, when executed, causes an access to an instruction, or to a literal operand [or] and an instruction [or both], said accessed literal operand or said accessed instruction being located at a predetermined position from a boundary of said instruction groups, said accessed instruction positioned at only the first location of an instruction group;

decoding said at least one instruction to determine at least said predetermined position of said accessed instruction as only the first location of the set of locations of the instruction group containing said accessed instruction;

locating at least said predetermined position; and

supplying said accessed instruction, or said accessed literal operand and said accessed instruction, from said instruction groups to said central processing unit, using [the] at least said predetermined [location, said operand or instruction or both to said central processing unit] position.