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Message: Re: VNS PORTFOLIO
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Dec 13, 2009 05:21AM

Seems Mr. Moore has re-defined the way computers (networks), and micro chips (individual multi-core computers) communicate with each other eliminating the need to communicate thru a common bus, thus eliminating or putting less importance on using the clock as a timing mechanism for instruction data.

This has been found by the inventor to provide important advantages. For example, since a clock signal does not have to be distributed throughout the computer array 10, a great deal of power is saved. Furthermore, not having to distribute a clock signal eliminates many timing problems that could limit the size of the array 10 or cause other known difficulties. Also, the fact that the individual computers operate asynchronously saves a great deal of power, since each computer will use essentially no power when it is not executing instructions, since there is no clock running therein.

If sucessful this may eliminate the need for our patents to a great degree in the future. This raises several questions. Is this Mr. Moore's way of getting even with TPL, or us? Did he work on this while he was the CTO of intellisys? Is this the real reason for his splitting with TPL in the first place? Will he use this as a ploy to align, or not, PTSC with him? Who will he use to enforce his patents, perhaps this will be used to bring TPL in tow. It would seem that his inventions corner the market on how micro-chips communicate efficently. Seems he may have the upper hand in negoiating with TPL.

I am no expert by far, and may be really off base here, but there may be some things we need to look at.

Also, as a further not he is using the same patent attorney as TPL, Mr. Henneman, does, or will this somehow again bring into light the possibility of a conflict of interest as in the past?

AJMO


Read more: http://www.faqs.org/patents/app/20090300334#ixzz0ZZozA6Sy

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