I attended the trial this afternoon, catching the later part of the testimony of TI witness - Dr. baher Haroun. He is one of the handful TI fellows. Texas Instruments OMAP 730 RISC Application Processor and DPLL was in the Q/A between him and both side of lawyers (HTC lawyer is Mr. Smith, did not catch name of out lawyers). I did not try to write down everything I heard. Here are some points I had some notes to say -

DPLL is digital type of PLL used in the TI chip (another kind is analog PLL). It operate in bybass mode and lock mode. In Lock mode,

DPLL output freqency = ckref (freqency of refference clock - the external clcok) * N (a interger 1-32) / N (a interger in 1-4). So the max output freqency is ckref * 32 / 1, and the min output freqency is ckref * 1 / 4.

There are two pin PDX3 and PDX4, if PDX3 is marked, it operate in lock mode; if PDX4 is marked, it operate in bypass mode.

Our lawyer asked him when the bypass mode is used. He said in power up. If using a cell phone as example, when power is up, it is in bypass mode. If user is sending a email, lock mode is in use. (these are not exact words since I'm not a recording machine).

When asked how fact the putput freqency, by 32 times? He said yse, many times.

Mr. Lockron was called to the stand our lawyer. I may gether my notes to post some stuff later.

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Now, I like to counter the following statement by you (Mark4321) -

"Dead zone or first power on (surge effect) on the VCO/ring oscillator frequency is not going to make a difference unless we can prove the source of the surge and the normal runing power is not from the output provide by the clocking crystal oscillator."

Dead zone do matter. In dead zone, cpu (or application processor in this case) is not dead. It is clocked by something. It's not external crystal clock, since its refrence signal is bypassed (and its too low in clocking rate). What else can clock the cpu? It has to be the ring oscilltor.

Second, the PLL is catching rising edge of the pulse wave of the crystal oscillator as the means to keep tracking the phases of both to PLL and external crystal clock, to keep them in sync. The crystal oscillator is not the source of current (or voltage) of PLL. At lease TI witness did not say that. If it is the source, then the VCO/ring oscillator and the cpu need to wait (cournt 0 to 30 - assuming max speed) to get the voltage or current. Who can keep VCO/ring oscillator and CPU dead in count 0 throgh 30)?

I find the following in a TI tech paper regard this -

http://www.ti.com/lit/an/scaa033a/scaa033a.pdf

So even if separate VCC and ground is doable, the increased jitter will make it impractical.

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D. Leckrone was called by our lawyer but the Q/A was not over. He will return on stand 9:AM tomorrow.

Saw Mr. Moore. The was a similar aged guy sitting at HTC table. I guess he may be Mr. Fish.