Aiming to become the global leader in chip-scale photonic solutions by deploying Optical Interposer technology to enable the seamless integration of electronics and photonics for a broad range of vertical market applications

Free
Message: History of CMOS process steps
Reply New Message
Prev Message Back To Forum Threaded View Next Message
  • Just a history on the scaling that I stumbled on and found kind of interesting that I wanted to share. I was curious since POET is reducing to 100 nm or less right off the bat and wanted to get an idea of how many reductions and how many years its been since Si was reduced below 100 nm.
  • 10 µm — 1971
  • 3 µm — 1975
  • 1.5 µm — 1982
  • 1 µm — 1985
  • 800 nm — 1989
  • 600 nm — 1994
  • 350 nm — 1995
  • 250 nm — 1997
  • 180 nm — 1999
  • 130 nm — 2002
  • 90 nm — 2004
  • 65 nm — 2006
  • 45 nm — 2008
  • 32 nm — 2010
  • 22 nm — 2012
  • 14 nm — 2013
  • 10 nm — est. 2015
  • 7 nm — est. 2017
  • 5 nm — est. 2019
    • 4 Recommendations
    Reply New Message
    Prev Message Back To Forum Threaded View Next Message
    Share
    Share
    New Message
    Please login to post a reply