I can think of 2 reasons PET will increase the speed of commercial chips:

1) Maing's reason is correct. Eventually the functionality of all chips on the device can be integrated onto one chip which will reduce size, but also simplify the way the separate components interact. The way I understand it, some components which are usually only included to facilitate communication between separate chips can be left out of the architecture.

2) GaAs has properties which make it inherently faster (i.e., the n-channel) and Taylor has devised a way of making the inherently slower parts (the p-channel) faster. So a complementary HFET can operate at speeds many times greater than Si CMOS. So even if Si has already achieved a size which is smaller than a GaAs transistor will ever be, that GaAs complementary HFET should be able to operate many times for every single operation in silicon. This means we shouldn't need such a high density as we require in silicon. In other words, while a CMOS chip could have 100 of billion transistors, a POET HFET operating at 10x the speed might only require 1 billion transistors to match it. Of course, POET is expected to be able to scale below the 100nm in time so the density of GaAs HFETs will add further speed increases in the years to come.

At least that's my understanding...