This week at the 2015 International Solid-State Circuits Conference (ISSCC), Intel will provide an update on its new 10nm manufacturing process and new research on how it's maintaining the march of Moore's law to 7nm and beyond. The first chips based on Intel's new 10nm process are expected in late 2016/early 2017, and the company says it's hoping to avoid the delays that haunted the belabored release of 14nm Broadwell. To hit 7nm, Intel says new materials will be required—as in, it looks like 10nm will finally be the end of the road for silicon. The most likely replacement for silicon is a III-V semiconductor such as indium gallium arsenide (InGaAs), though Intel hasn't provided any specific details yet.

ISSCC 2015, being held in San Francisco this week, is where all the big players in silicon (Intel, Samsung, TSMC, IBM, etc.) meet to talk about their latest manufacturing processes and how they might go about overcoming the current barriers to smaller, faster, and denser computer chips. It's not unusual for Intel to have one of the largest presences at the conference, and this year is no different: it will be presenting three papers on its 14nm technology, hosting sessions on a variety of topics, and Mark Bohr—one of Intel's most esteemed researchers—will be sitting on a panel that discusses Moore's law beyond 10nm.

On a conference call last week, Intel gave reporters a preview of what to expect at ISSCC, along with some updates on its upcoming 10nm process and the difficult step down to 7nm. On the call, Intel acknowledged that its Broadwell chips were delayed due to the unforeseen complexity of manufacturing at 14nm, but the company says it hopes to avoid the same delays with 10nm, even though it will require even more steps than 14nm.

More interesting than 10nm, though, is the news that Intel is looking to move away from silicon FinFETs for its 7nm process. While Intel didn't provide any specifics, we strongly suspect that we're looking at the arrival of transistors based on III-V semiconductors. III-V semiconductors have higher electron mobility than silicon, which means that they can be fashioned into smaller and faster (as in higher switching speed) transistors. The topic of extreme UV (EUV) lithography also came up during the call, but due to continued problems with EUV deployment, it sounds like Intel is planning to do both 10nm and 7nm without it.

Due to other constraints—thermals, power consumption, and form factor—Intel is also looking into new types of packaging: 2.5D, where separate dies are placed side by side on an interposer, and 3D, where each die is stacked directly on top of each other. Both 2.5D and 3D packaging are good for reducing power consumption, with 3D really coming into its own with mobile and wearable devices.

With 10nm, Intel hopes to carry the mantle of Moore's law forward to yet another node while continuing to decrease the price per transistor—in other words, we'll continue to see chips that consume slightly less power while also integrating yet more features onto a single die. 7nm, with a possible shift away from silicon, is more exciting; transistors fashioned out of III-V semiconductors can consume much less power while switching at much higher speeds. Individually, neither of these new processes are likely to raise the roof; but a 3D stack of 7nm dies... now we're talking.