This news release form October 22nd doesn't even mention 3-inch wafer scale, and notice the references to customer needs.

So, maybe BAE and GloFo are working together in the same style Samsung and GloFo collaborate? Exchanging design enablement kits as they move forward? Verifying critical foundation devices?

October 22nd, 2014

Toronto, ON, and Storrs, CT, October 22, 2014 – POET Technologies Inc. (TSX-V: PTK and OTCQX: POETF) (the “Company”) – developer of the planar opto-electronic technology (“POET”) platform for monolithic fabrication of integrated circuit devices containing both electronic and optical elements on a single semiconductor wafer – today announced several key updates on its “Lab-to-Fab” transition and its 100-nm and 40-nm scaling program and several operational updates.

“Lab-to-Fab” Transition: 100-nm and 40-nm Scaling Program Update

The Company recently reported a contractual effort with a “3rd party foundry” to accelerate the transition from “Lab-to-Fab” of the POET technology to a manufacturing status at the 6” wafer scale. The target of the effort is 40-nm dimensions for the critical features. This engagement will support and enhance the development and verification of the foundation devices and design enablement kits. Additionally it will provide the baseline FEOL (Front End Of Line) process flow in a manufacturing environment and toolset. Fabrication at 40-nm (Silicon CMOS) is a mature semiconductor process that has been in existence since 2007-2008. This enables POET to target a mature process flow and revitalize existing manufacturing lines while delivering predicted performance and power efficiencies that rival today’s state of the art process node in the sub 20-nm range (Silicon CMOS). This effort will enable and progress two of our current key initiatives which the Company is currently working on, a 100-nm ring oscillator which is a common demonstration vehicle for performance and an integrated 50GHz VCSEL device, both targeted for Q1 of 2015.

Recently, milestone goals and their associated target completion dates have been adjusted to align to potential customer demands. Mr. Peter Copetti, Executive Chairman and Interim CEO noted: “It is important for us to remain flexible in setting design targets to the market. The Company is focused on delivering to its potential customers the technology nodes that will enable them to leapfrog their competition. Our “Lab-to-Fab” transition and our new 40-nm target node will deliver just that: a roadmap for integrating electrical and optical capabilities, performance and power efficiency.”

Operational Updates

The Company is anticipating delivery of the 40-nm PET Process Design Kits (PDKs) by the end of the year. The Company is using Synopsys TCAD tools and services to develop the PET and POET PDKs. PDKs are used by 3rd party chip developers to create IP libraries that would be used to implement System on Chip (SoC) integrated circuits. Availability of the PDKs will enable early evaluation of the performance advantages of POET technology and design of IP required for SoC implementation. Daniel DeSimone, the Company’s Chief Technology Officer noted: “We are encouraged by our progress on the PDK development and our level of collaboration with the Synopsys team. This level of modeling is synergistic to our parallel efforts with our 3rd party foundry on the development of 100-nm and 40-nm process flow.”

The Company’s website and the corporate presentation have been updated to highlight the new targets set forth from the management team that reflect customers and market expectations. The value proposition of the company is strong with the new 40-nm feature size target predicted to operate 4 nodes better in logic performance and 3 nodes better in power consumption compared to Silicon CMOS. The density is expected to be comparable and possibly better, as POET requires less buffering and upsizing of logic cells. The POET process offers the ability to have digital, analog and mixed signals and optical devices on the same die or chip. Those capabilities would allow designs of complex systems and SoC (Systems on a Chip) to deliver innovations and integration that are impossible today with existing processes in the market. This process node also takes advantage of existing and mature manufacturing capabilities already available in the industry.