I noticed something interesting, I don't think it's been mentioned before?
Check out "sense amplifier", it's very interesting how POET solves this redundancy in memory cells.

https://en.wikipedia.org/wiki/Sense_amplifier

The configurable nature of the thyristor memory cell as a static memory cell or a non-volatile memory cell has many advantages, including:

The same footprint of memory cell is used.

For high speed function, the SRAM operation can be used.

NV backup operation can be used for certain power modes (i.e., for low-power sleep state or upon sudden loss of power).

The thyristor memory cell can also operate a DRAM cell. This is shown in FIG. 5. The states are the same as the SRAM but there is an additional state called the “store” state. Thus, after writing either a volatile “1” or “0” bit value, and during the time that a read operation is not required (these represent substantial periods of time when neither writing nor reading are necessary), the word lines of the respective thyristor memory cells are powered down to a low voltage (e.g., approximately 0.6V), which is labeled “Dynamic Storage State” in FIG. 5. The charge in the quantum well interfaces 11, 14 cannot escape by conduction because the components have been reduced drastically. Also recombination is essentially zero. Therefore, if a volatile “1” bit value is stored by the memory cell, i.e., the quantum well interfaces 11, 13 of the thyristor device of the thyristor memory cell are filled with charge, the quantum well interfaces 11, 13 will remain filled for a long time. Simulations have shown that when the voltage is raised back to the level of the SRAM volatile “1” bit value after 1 msec, there is still enough charge left in the thyristor memory cell to restore the ON state. That means the data has not been lost. If the store time exceeds some long time, say 1 msec, then sufficient charge leaks away that a volatile “0” bit value will be obtained upon increasing the voltage. So a refresh operation is required periodically (e.g., once every msec) as shown in FIG. 6. The advantage gained is ultra-low power. The speed of read and write is identical to the SRAM. Clearly this DRAM has significant advantages which are:

same speed as the SRAM operation.

selective operation of the cell as an SRAM cell or DRAM cell can be controlled by simply disabling the refresh cycle and the store voltage.

the NV backup operation can also be used here as well.

extremely low power operation is possible.

extremely high density is possible.

complex sense amplifiers are not required; the thyristor action is its own sense amplifier and provides a digital output signal on the respective bit line.

not limited by stored charge as in conventional DRAM; the thyristor is an active device which can supply current instead of charge—active read.