http://www.eetimes.com/document.asp?doc_id=1326904

,,The CELO approach resulted in gate-first self-aligned FinFETs with excellent electrical characteristics which outperformed similar sized silicon transistors. The InGaAs FinFETs had 100nm long gates, 50nm wide fins, 250nm wide contacts and was 30nm thick. Since no processes other than standard CMOS were used, IBM claims the III-V on silicon CELO technology has "significant potential" for high-volume manufacturing at advanced CMOS nodes."