Aiming to become the global leader in chip-scale photonic solutions by deploying Optical Interposer technology to enable the seamless integration of electronics and photonics for a broad range of vertical market applications

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  • Demonstrator chip fabricated in 28nm FDSOI (Mar. 2014)

    • – Showcased suite of novel low power design techniques

    • – Power savings confirmed - well correlated with simulation

    • – Variability tolerance designed in to maximise manufacturing robustness

    SUMMARY

    • Ultra Low Power SP SRAM developed for 28nm FDSOI

      – Dynamic power savings >50%
      – Static power savings >20% (much more with back bias)

    • High Performance at Low Voltages

      – Simulated down to 0.7V
      – 450MHz cycle time

    • Available end Q2’15

    • Customisation possible

    • Flexible engagement model


    >> FDSOI provides elegant transition from bulk CMOS


    http://www.soiconsortium.org/fully-depleted-soi/presentations/january-2015/sureCore%20FDSOI%20Consortium%20Tokyo%20Jan15%20For%20Publication.pdf


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