Demonstrator chip fabricated in 28nm FDSOI (Mar. 2014)

• – Showcased suite of novel low power design techniques

• – Power savings confirmed - well correlated with simulation

• – Variability tolerance designed in to maximise manufacturing robustness

• Ultra Low Power SP SRAM developed for 28nm FDSOI

  – Dynamic power savings >50%
  – Static power savings >20% (much more with back bias)

• High Performance at Low Voltages

  – Simulated down to 0.7V
  – 450MHz cycle time

• Available end Q2’15

• Customisation possible

• Flexible engagement model