FD-SOI Vs. FinFETs

APRIL 16TH, 2015 - BY: ED SPERLING

Semiconductor Engineering sat down to compare the benefits, risks and challenges of moving to finFETs compared with fully depleted silicon on insulator (FD-SOI) with Philippe Magarshack, group vice president for technology R&D atSTMicroelectronics; Marco Brambilla, director of engineering at Synapse Design; Mike Stuber, vice president of device engineering at Silanna; Wayne Dai, chairman and CEO of VeriSilicon; Naim Ben-Hamida, senior manager of mixed signal design and test at Ciena; Kelvin Low, senior director of foundry marketing at Samsung Semiconductor; Amir Bar-Niv, senior group director of design IP marketing atCadence; and Mike McAweeney, senior director of product solution sales atSynopsys. What follows are excerpts of that conversation.

SE: Why do we need FD-SOI at 28nm?

Low: It’s all about power and cost. Having solutions optimized for both is necessary. FinFETs also are coming into play for meeting system requirements, and we see customers using this for some of their products. But for many other products, such as IoT and wearables, cost sensitivity and ultra-low power dictate that finFETs may not be suitable. FD-SOI presents a very good opportunity, and the solution is already in place.

Bar-Niv: What we hear from our customers is that with FD-SOI, it’s all about power. We hear about cost, too, but people are still debating whether cost will really be lower. There is less involved in the process, which could make it cheaper than bulk, but this depends on the foundry. Power is the dominant factor for this technology.

Brambilla: We’re developing an IoT device. Without this technology, I wouldn’t have a product. It would have to be developed in 40(nm) and work at 1 volt. It wouldn’t meet timing. Even if the scaling isn’t normally what you would associate with 28nm, the reason we chose it is that we have to run off a very small battery. Leakage control is the thing to do. The technology allows such huge voltage swings that we can waste power only when we need to. With other technologies we would not have that latitude with Vdd.

Magarshack: The problem we set out to solve initially was that application processing for cell phones has a wide range of operating modes, either very high speed or high voltage or high power, which are traditional solutions. This is a very short period of time. Most of the time they are sitting idle or at medium processing performance. Because the application processor lives off batteries, how do you minimize power in this workload? This is where FD-SOI comes in. It’s an extremely wide space for tradeoffs between voltage, Vdd voltage for back bias, and implementations come in very handy. With the same chip, we can address two product segments. One is the very high end performance. The other is ultra low power/low voltage. We can turn the knob and address those product segments with the same silicon.

Ben-Hamida: We need both high-performance analog and high-speed at the same time large processing capability. It gives us the high-speed performance and the scaling benefits of a large DSP.

Dai: For the first time, cost per transistor is going up. Moore’s Law may continue, but it’s under stress. We have absolutely hit a wall, and whenever that happens. The choices are 2.5D, 3D, finFETs or FD-SOI. People are looking at good alternatives below 28nm for the IoT and wearables, but if they need mixed signal then finFETs aren’t a very good solution. This is the landscape you need to look at. The leaders will take one choice because they move earlier, but it may not be the right one for applications like IoT.

McAweeney: We talk to a lot of customers about a lot of different applications and power always comes up. Some customers are saying they need a lower-power device, and FD-SOI gives you the opportunity to run things at a lower voltage. Other customers say they need high performance for a very short amount of time, then do always-on sensing at very low power. So they need low power plus the ability to serve a wide range of uses.

SE: So why FD-SOI versus a low-power process at 28nm? Is it that much better? And is it better than finFETs, or is that simply a matter of cost?

Low: If you look at FD-SOI versus other variants of 28nm, there is an issue of cost sensitivity. If cost is a boundary for decision-making, things will be different. If you look at certain segments of the IoT, such as wearables, they’re very cost-sensitive. Compared to other variants of 28nm, the cost factor and the ability to use a much lower power supply and the flexibility of the body biasing are very important. FD-SOI offers the lowest power and the lowest leakage at the right cost point. From the foundry side, other processes have pros and cons.

Brambilla: Going to a smaller node would have severely penalized us because we didn’t have enough stuff to put into the die. On the other 28nm nodes, nothing offered the same power level we can get with FD-SOI. Whether you’re running at 50 watts or 50 milliwatts, your techniques are the same. Unless you need to do something super fast with a specialized processor, what you are doing is exactly the same even though it looks different from the outside.

Dai: Bulk has different leakage specs for 28nm. You can still use low voltage, even though it’s a stretch, but you can’t use it with high voltage because the leakage is really bad.

Low: If the product needs to run at a certain frequency number, there will be limitations on FD-SOI. You need to understand what the product objectives are to make the right decision about which process to use. There will be some high-end performance applications that FD-SOI will not be able to satisfy.

SE: How much of a seamless continuation of design approaches is this? Designers have been using body biasing for awhile, but the latest twist is forward and back biasing.

Magarshack: The additional design knob is good to have, but it does take some getting used to. It does open up new avenues, and this is the knob that enables the same product to be adequate for higher performance and high power, as well as lower power, lower performance but lower voltage. At the same time it’s an interaction of the application and the body bias, and to take advantage of that you need to be sure you don’t throw off the voltage connection to that. So there are some strings attached. We are working with some EDA vendors to make it as transparent as possible. You need to be aware of these things going on, especially if you are working on the physical implementation of the die. But it is the price you pay to get to full performance and minimize power and voltage. At the same time, you can save in area because you don’t have to overdesign as much.