As Moore’s Law Slows, Hedge Your Bets With Design Process Efficiency
posted on
Sep 21, 2015 10:28AM
interesting information......
Posted by Kurt Shuler on Thu, Sep 17, 2015 @ 11:34 AM
.....Are you dreading the day when Moore’s Law comes to a grinding halt? I’m concerned, but I’m not as fatalistic as some.
Here’s why: There are plenty of ways to eke out more scalability in the semiconductor design process through greater efficiency.
SoC design realities make it imperative to re-evaluate mature semiconductor processes for greater efficiencies that yield lower costs, higher performance and shorter time to market. Because scaling to lower geometries won’t yield the same economic or technological benefits that have fueled the semiconductor industry in the past, it’s time to consider what else is possible to sustain innovation and growth.
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In other words, the industry needs to refocus its energies on optimizing the initial design of a chip, rather than betting on future process node shrinks to meet cost, performance and power goals.
Some teams already have adopted this approach, and below are some quantifiable benefits of an improved SoC design process:
The teams that cling to internal interconnect efforts are struggling to achieve these optimizations. They rely on legacy technology, hierarchal buses and configurable crossbars. These efforts have not been able to keep pace with rising SoC complexity during the steady march toward 14nm.
Engineers adopting advanced NoC IP in their design have been able to see the benefits. NoC interconnect fabric IP is one of the few areas left on the SoC that is configurable. Internal efforts are inevitably falling by the wayside because IP content is rising and teams assigned to the interconnect development task cannot keep up with the late stage changes and rising complexity.
Designers looking to hedge against Moore’s Law slowdown, should consider the interconnect technology that drives highest quality of results. Lower product cost and hardware architecture flexibility should rate equally high on any priority list. NoC IP is best qualified for simultaneously improving quality of results and productivity.
http://info.arteris.com/blog/as-moore-s-law-slows-hedge-your-bets-with-design-process-efficiency