posted on
Mar 06, 2018 01:40PM
Aiming to become the global leader in chip-scale photonic solutions by deploying Optical Interposer technology to enable the seamless integration of electronics and photonics for a broad range of vertical market applications
Message: POETF
interesting connection to Accelink......from July 2016
A*Star launches silicon photonics and MEMs packaging consortia
07/26/2016
The A*STAR Institute of Microelectronics (IME; Singapore) has launched two consortia for advanced packaging: the Silicon Photonics Packaging consortium (Phase II) and the MEMS Wafer Level Chip Scale Packaging (WLCSP) consortium. Each will develop novel solutions in the heterogeneous integration of MEMS and silicon photonics devices, which will improve overall performance and reduce production costs.
In Phase I of the Silicon Photonics Packaging Consortium, IME and its industry partners had developed new capabilities in device library and associated tool boxes to enable the integration of low profile lateral fiber assembly, laser diode, and photonics devices. By employing a laser welding technique, the consortium demonstrated a fiber-chip-fiber loss of less than 8 dB with less than 1.5 dB excess packaging loss.
In Phase II, the Consortium will further develop low loss silicon coupling modules, and provide a series of packaging solutions for laser diode integration. It will also focus on developing accurate thermal models, as well as improve overall module thermal management, reliability, and RF performance to meet very high data bandwidth demand. All these developments will lead to a more integrated packaging solution that promises better assembly margins and lower module costs. Members of the consortium include: Accelink Technologies, Corning, Fujikura, Fraunhofer Heinrich Hertz Institute, and NTT.
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