GT part two
posted on
Sep 04, 2018 01:38AM
the international patent for theTaylor/Jianhong and INTOP patent published on Aug 23
Pub. No.: |
WO/2018/156679 |
International Application No.: |
PCT/US2018/019095 |
Publication Date: |
30.08.2018 |
International Filing Date: |
22.02.2018 |
Applicants: |
INTOP CORP.[US/US]; P.O. Box 134 Wilton, NH 03086, US |
Inventors: |
TAYLOR, Geoff, W.; US CAI, Jianhong; US |
(EN) INTEGRATED CIRCUIT IMPLEMENTING A VCSEL ARRAY OR VCSEL DEVICE
(EN) A semiconductor device includes a plurality of VCSEL devices (or VCSEL device) formed from a layer structure that includes bottom n-type layer(s), intermediate p-type layer(s), an n-type modulation doped quantum well structure formed above the intermediate p-type layer(s), at least one spacer layer formed between the intermediate p-type layer(s) and the n-type modulation doped quantum well structure, and top p-type layer(s). An annealed oxygen implant region is disposed vertically within the at least one spacer layer and an annealed n-type ion implant region is disposed vertically within the top p-type layer(s). Both ion implant regions can surround and extend laterally in a continuous manner between a plurality of VCSEL devices for current funneling and isolation. Furthermore, built-in hole charge Qp for the intermediate p-type layer relative to built-in electron charge Qn for the bottom n-type layer can be configured for diode-like current-voltage characteristics of the VCSEL device(s).