Shash congrats on achieving HL status. I do have a question for you however.

You have spoken of yield issues that POET is trying to resolve. Is this something that you have heard from the company or read somewhere or is it something you have assumed? If you have heard this from an official source can you provide some insight into the issue? I know that yield is  more an issue associated with shrinking node size to fit more logic elements onto a wafer but the optical stuff that POET is working at and the high frequency RF traces are really at much larger scale so really I would not have thought yield should be a problem?

What I have visualized as potentially having difficulty is associated with insertion loss where lining up the waveguide and spot size converter butt connections could be reduced in accuracy as a result of variations in the stops. But they seem to be targeting levels of accuracy which puts losses at well below existing processes/standards. If this was a problem I would expect that they would be satisfied to just achieve the requirement and not something better after all cost is the main disruptor. Again this is all being done at very large scale using simple lithography as provided by what the company has presented.