It is impressive to see what I consider to be the generations (embodiments) of the platform presented in this granted patent. We have all I think become familiar with POET’s typical configuration of both electrical die and photonic die 3d bonding to the electrical interconnects on the  substrate which contains the metal conductors required for electrical connection of both the electrical and optical dies. But there is another generation here that has not been talked about or represented in any of POET’s corporate presentations.

 In some embodiments, transistor arrays 764 in the substrate 710, are used for signal processing, signal conditioning, signal generation, memory, and computation,

So there are a couple configurations in which electrical functions are imbedded in the substrate as identified above rather than a 3d bonded electrical die to the electrical interconnect layer.

Just thought I would bring it to people’s attention because it I believe it represents the versatility of this platform for numerous future applications.