From one of  my older posts.

Ayar Labs has identified a “zero-change” process at 45 nm/32 nm SOI. That is a really hard act for photonic element integration at such small nodes in so many ways. So if you are going to integrate all but the lights sources at these nodes all the improvements since those nodes were developed are left behind and that gap will continue to widen.

The degree of wavelength accuracy becomes really difficult the narrower a waveguide has to become in order to fit on a silicon die at such small nodes. Wavelength error is directly proportional to waveguide size deviation.

Consider this. Single mode fiber is 9000nm in diameter or about 1/10th of a human hair.   If you are building waveguides at 1000nm a deviation of 1 nm in the width of that waveguide creates and error of .001 if a waveguide is built at 100nm that same 1 nm deviation produces an error 10 times greater. And then we have thermal cross talk between waveguides. Don’t get me started on that one.

There is a reason why the big guns have come out with a co-packaged collaboration. Customers want a solution and need to start steering that boat. POET has a vessel that looks really compelling and the man running that ship knows how to develop leading edge technology. We are on the right path people and this ship is getting ready to sail.