Aiming to become the global leader in chip-scale photonic solutions by deploying Optical Interposer technology to enable the seamless integration of electronics and photonics for a broad range of vertical market applications
Message: Comments from Juniper Sr Director of Engineering on Lightelligence at Hot Chips
Lightelligence reposted this
2d • Edited •
Every time I attend Hot Chips, I secretly wish that I would learn about some new innovative idea that could be a game changer.
This time, I came across one such presentation from the startup Lightelligence on Photonic interposers. Most of us know what a silicon interposer is. It is basically a thin layer of silicon-based material that sits above the package substrate. It acts as a conduit for high-speed signals between the ICs placed above it. Originally, it was used for communication between a chiplet and HBM in 2.5D packages. With recent advances in the maximum interposer sizes, these interposers are also used for communication between the chiplets.
This company takes this concept further by introducing photonic integrated circuits as active interposers to transmit data between the chiplets (or ICs) using waveguides. The electrical signal is converted into the optical signal inside the active interposer, and communication between the ICs is in the optical domain.
While the merits of this complex and advanced circuitry are debatable at smaller package sizes, like the prototype they have built, we all know that every technology starts from foundational steps, and it is through subsequent innovations that a broader significance emerges.
If this technology can scale to wafer scale integration, that could be a game changer, IMO. Take the 2D/3D Torus network used by Google. Currently, they use electrical interconnects for the TPUs inside and the optical circuit switches at the edges to create multiple topologies inside the pod. What if, sometime in the future, the uncut TPUs on a wafer with a wafer-scale photonic interposer underneath use the optical domain for all the connectivity in the Torus? That may help create more complex topologies with low latencies and would be efficient in power too. A similar concept could be extended to larger packages with GPUs.
More innovation needs to happen for building large PIC interposers and efficient waveguide crossings etc., before this technology brings in significant savings. But, good to see these innovations around improving chiplet interconnects.
Happy Friday!
This time, I came across one such presentation from the startup Lightelligence on Photonic interposers. Most of us know what a silicon interposer is. It is basically a thin layer of silicon-based material that sits above the package substrate. It acts as a conduit for high-speed signals between the ICs placed above it. Originally, it was used for communication between a chiplet and HBM in 2.5D packages. With recent advances in the maximum interposer sizes, these interposers are also used for communication between the chiplets.
This company takes this concept further by introducing photonic integrated circuits as active interposers to transmit data between the chiplets (or ICs) using waveguides. The electrical signal is converted into the optical signal inside the active interposer, and communication between the ICs is in the optical domain.
While the merits of this complex and advanced circuitry are debatable at smaller package sizes, like the prototype they have built, we all know that every technology starts from foundational steps, and it is through subsequent innovations that a broader significance emerges.
If this technology can scale to wafer scale integration, that could be a game changer, IMO. Take the 2D/3D Torus network used by Google. Currently, they use electrical interconnects for the TPUs inside and the optical circuit switches at the edges to create multiple topologies inside the pod. What if, sometime in the future, the uncut TPUs on a wafer with a wafer-scale photonic interposer underneath use the optical domain for all the connectivity in the Torus? That may help create more complex topologies with low latencies and would be efficient in power too. A similar concept could be extended to larger packages with GPUs.
More innovation needs to happen for building large PIC interposers and efficient waveguide crossings etc., before this technology brings in significant savings. But, good to see these innovations around improving chiplet interconnects.
Happy Friday!
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