remember, the full formula is

ic cost = (die cost + test cost + packaging cost) / final test yield

with GaAs, POET die cost is probably going to be higher until volume ramps up (and even then, wafers would still be higher cost than silicon).

similarly, although the wafers are more fragile (relatively speaking, ref. Wavetek's direct experience, pdf linked in one of my posts yesterday), the physical yield and defect rate will be initially higher with improvement over time. that Wavetek/UMC is in business to make money tells you their volume manufacturing abilities are competitively profitable.

but (and it's a very big but) in POET's favor?

the test and packaging costs will each be significantly lower, in many cases by several orders of magnitude. 10x 100x 1000x, depending on the IC's intended end use.

this deck is a bit old, but gives you a great overall idea of the types of costs involved.

although we don't know the size of any target dies ("chips") you can play around with some good calculators here or here, which will provide real data, if that's something that floats your boat.

GLAL,

R.