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Message: Re: Pacer:e.DIGITALv Intel - Intel petition USPTO for Interparte exam of 108 patent!
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U.S. PATENT NO. 5,839,108

http://www.google.com/patents/US5839108

Claim 1

What is claimed is:

1. A method of memory management for a primary memory created from a non-volatile, long-term storage medium, said method enabling direct manipulation of contiguous and non-contiguous discrete data segments stored therein by a file system, and comprising the steps of:
(a) creating the primary memory from a non-volatile, long-term storage medium, wherein the primary memory comprises a plurality of blocks in which the data segments are to be stored;
(b) coupling a cache memory to the primary memory, said cache memory providing temporary and volatile storage for at least one of the data segments;
(c) writing a new data segment from the cache memory to the primary memory by linking said new data segment to a sequentially previous logical data segment by the following steps:
(1) receiving the new data segment in the cache memory;
(2) moving the new data segment from the cache memory to a next available space within primary memory such that the new data segment is stored in primary memory in non-used memory space;
(3) identifying the previous logical data segment in primary memory;
(4) creating a logical link between the previous logical data segment and the new data segment such that the logical link provides a path for sequentially accessing the data segments within the primary memory;
(5) creating additional serial and logical links as subsequent new data segments are written to primary memory, said logical links providing the path for serially accessing the data segments regardless of contiguity of the data segments relative to each other within the primary memory; and
(6) storing the data segments to primary memory in a manner consistent with an industry standard data storage format while retaining linking between data segments created in previous steps.
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