I have included this previous post from DNWL, which explains that Galium Arsenide is more brittle than silicon in the production of the wafer.

http://agoracom.com/ir/POETTechnologies/forums/discussion/topics/610716-gallium-arsenic-and-old-lake/messages/1915060#message

My understanding is that the POET IP is to the process on the circuit and not the actual fabrication. POET are fabless, therefore the responsibly to address this concern lies more with the fabrication partner. There are already techniques in practice to resolve this issue as described in the link.