DONI , Eventually we should get them on all CMOS based digital camcorder !
old news but interesting connection
Flash memory option for baseline CMOS
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PHILIPS Electronics has announced a new Flash memory option, available from Adilam Electronics , for its 0.18µm CMOS18 baseline CMOS process.
By allowing designers of ASICs, SoCs and embedded controllers to implement large amounts of Flash memory in a very small area of silicon, the new CMOS18-FFLV (Fast-Flash, Low-Voltage) option meets industry demand for increased non-volatile data storage.
Offering memory densities approaching 1Mb per square millimetre of silicon and ultra-low power consumption, CMOS18-FFLV implements the smallest area Flash memory blocks in the industry. The result is lower chip cost together with enhanced memory performance.
The ultra-low power consumption of Philips' new embedded Flash is the result of an innovative floating-gate memory cell that utilises Fowler-Nordheim tunneling for both programming and erasure.
This eliminates the high-current charge-pump required for 'channel hot-electron' programming (the technique used in most other embedded Flash technologies) and therefore saves a considerable amount of silicon area.
Largely insensitive to supply voltage changes, Philips CMOS18-FFLV embedded Flash memory operates over a wide supply voltage range - from voltages as low as 1.2V to voltages as high as 2.0V - making it suitable for use in battery-powered applications.
An EEPROM version of the memory that will offer single-byte erasure and re-programming is currently under development.
To ease the integration of Flash memory into SoC solutions based on ARM processors (now the leading embedded processor architecture for many target applications) Philips has designed a special interface for CMOS18-FFLV embedded Flash that simplifies connection to the ARM system bus.
It has also developed specific IP to enable testing, in-system programming and production-line programming of the memory through a single JTAG interface.
Standardisation of the test interface has also helped to reduce the time, cost and effort involved in generating e-sort (wafer-level) test programs for ASIC and SoC products that use this new embedded memory option.
Developed as part of the MEDEA+ initiative, CMOS18-FFLV is already qualified for production, enabling chips with embedded Flash to be delivered in volume later this year.
The option will also be supported in Philips' CMOS18 process shrink to 0.15µm geometry
